Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9767638 | Slot machine that increases the number of displayed symbols and control method thereof | Yutaka Kadode, Masahiro Yoshida, Hiroyuki Kuroyanagi, Satoshi Watanabe, Yuka Hotta +2 more | 2017-09-19 |
| 9378625 | Gaming machine with sound output for specific symbol and control method thereof | Taihei Abe, Koutarou Moriyama, Toshiaki Ohkubo, Shigeki Hayashi, Yuka Hotta +2 more | 2016-06-28 |
| 9183699 | Gaming system with common display and control method of gaming system | Kenichi Fujimori, Arata Ajiro | 2015-11-10 |
| 8911289 | Gaming machine comprising indicating device showing territory determined by gaming result | Mitsuhiro Takeda, Takeshi Aoki, Tomoyuki Hasegawa, Shintarou Okazawa, Takanori Sakata +1 more | 2014-12-16 |
| 8858320 | Slot machine that increases the number of displayed symbols and control method thereof | Yutaka Kadode, Masahiro Yoshida, Hiroyuki Kuroyanagi, Satoshi Watanabe, Yuka Hotta +2 more | 2014-10-14 |
| 8382571 | Gaming system with common display and control method of gaming system | Kenichi Fujimori, Arata Ajiro | 2013-02-26 |
| 8257167 | Gaming system for playing common game in groups and control method thereof | Kenichi Fujimori, Arata Ajiro | 2012-09-04 |
| 5671379 | System and method for managing windows | Kazushi Kuse, Kinichi Mitsui, Shahram Javey | 1997-09-23 |
| 5602770 | Associative memory device | — | 1997-02-11 |
| 5416747 | Semiconductor memory driven at low voltage | — | 1995-05-16 |
| 4989182 | Dynamic random access memory having dummy word line for facilitating reset of row address latch | Hirohiko Mochizuki, Yukinori Kodama, Meiko Kobayashi, Takaaki Furuyama | 1991-01-29 |
| 4970693 | Semiconductor memory device with internal control signal based upon output timing | Shigeki Nozaki, Masaru Satoh, Tomio Nakano, Yoshihiro Takemae | 1990-11-13 |
| 4905201 | Semiconductor memory device capable of selective operation of memory cell blocks | Tomio Nakano | 1990-02-27 |
| 4870617 | Semiconductor memory device having data bus reset circuits | Masao Nakano, Hirohiko Mochizuki, Yukinori Kodama, Hidenori Nomura | 1989-09-26 |
| 4821232 | Semiconductor memory device having data bus reset circuit | Masao Nakano, Hirohiko Mochizuki, Yukinori Kodama, Hidenori Nomura | 1989-04-11 |
| 4806795 | Transfer gate circuit protected from latch up | Masao Nakano, Hidenori Nomura | 1989-02-21 |
| 4807192 | Memory device employing address multiplexing | Masao Nakano, Hirohiko Mochizuki, Yukinori Kodama, Hidenori Nomura | 1989-02-21 |
| 4799197 | Semiconductor memory device having a CMOS sense amplifier | Yukinori Kodama, Hirohiko Mochizuki, Masao Nakano, Hidenori Nomura | 1989-01-17 |
| 4583204 | Semiconductor memory device | Yoshihiro Takemae, Shigeki Nozaki | 1986-04-15 |
| 4550289 | Semiconductor integrated circuit device | Katsuhiko Kabashima, Yoshihiro Takemae, Shigeki Nozaki, Hatsuo Miyahara, Masakazu Kanai +1 more | 1985-10-29 |
| 4532613 | Semiconductor memory device | Yoshihiro Takemae, Tomio Nakano | 1985-07-30 |
| 4504929 | Dynamic semiconductor memory device | Yoshihiro Takemae, Seiji Enomoto | 1985-03-12 |
| 4484312 | Dynamic random access memory device | Tomio Nakano, Masao Nakano, Yoshihiro Takemae, Norihisa Tsuge | 1984-11-20 |
| 4450515 | Bias-voltage generator | Yoshihiro Takemae, Tomio Nakano, Masao Nakano, Norihisa Tsuge | 1984-05-22 |