Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10741249 | Word all zero memory | — | 2020-08-11 |
| 9762261 | Error detection and correction in ternary content addressable memory (TCAM) | Thomas R. Wik | 2017-09-12 |
| 9722605 | Low leakage and data retention circuitry | Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Andrew Cole | 2017-08-01 |
| 9529669 | Error detection and correction in binary content addressable memory (BCAM) | Thomas R. Wik | 2016-12-27 |
| 9350349 | Low leakage and data retention circuitry | Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Andrew Cole | 2016-05-24 |
| 8854077 | Low leakage and data retention circuitry | Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Andrew Cole | 2014-10-07 |
| 8416633 | SRAM leakage reduction circuit | Michael Tooher | 2013-04-09 |
| 8355269 | Pushed-rule bit cells with new functionality | — | 2013-01-15 |
| 8253438 | Low leakage and data retention circuitry | Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Andrew Cole | 2012-08-28 |
| 8077527 | SRAM leakage reduction circuit | Michael Tooher | 2011-12-13 |
| 7940081 | Low leakage and data retention circuitry | Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Andrew Cole | 2011-05-10 |
| 7684262 | SRAM leakage reduction circuit | Michael Tooher | 2010-03-23 |
| 7592837 | Low leakage and data retention circuitry | Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Andrew Cole | 2009-09-22 |
| 7443197 | Low leakage and data retention circuitry | Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Andrew Cole | 2008-10-28 |
| 7348804 | Low leakage and data retention circuitry | Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Andrew Cole | 2008-03-25 |
| 7227383 | Low leakage and data retention circuitry | Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Andrew Cole | 2007-06-05 |
| 7051308 | Method and apparatus for integrated circuit design with library cells | Michael J. McManus, Billie J. Rivera, Richard Talburt, William G. Walker | 2006-05-23 |
| 6839882 | Method and apparatus for design of integrated circuits | Michael J. McManus, Billie J. Rivera, Richard Talburt, William G. Walker | 2005-01-04 |
| 6766496 | Method and apparatus for integrated circuit design with a software tool | Michael J. McManus, Billie J. Rivera, Richard Talburt, William G. Walker | 2004-07-20 |
| 5625797 | Automatic optimization of a compiled memory structure based on user selected criteria | Thomas V. Ferry, Russell L. Steinweg, Pei-Hu Lin | 1997-04-29 |
| 5596505 | Estimation of pin-to-pin timing for compiled blocks | Russell L. Steinweg, Pei-Hu Lin | 1997-01-21 |
| 5349552 | Memory compiler with multiple selectable core elements | — | 1994-09-20 |
| 5245584 | Method and apparatus for compensating for bit line delays in semiconductor memories | Hai Phuong | 1993-09-14 |
| 5231311 | Digital output buffer and method with slew rate control and reduced crowbar current | Thomas V. Ferry, Jamil Kawa, Kerry M. Pierce, William G. Walker, James S. Hsue | 1993-07-27 |
| 5111075 | Reduced switching noise output buffer using diode for quick turn-off | Thomas V. Ferry, Jamil Kawa, Kerry M. Pierce, William G. Walker | 1992-05-05 |