Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6757854 | Detecting faults in dual port FIFO memories | Jun Zhao, Mukesh K. Puri | 2004-06-29 |
| 6681358 | Parallel testing of a multiport memory | Farzin Karimi, Thompson W. Crosby | 2004-01-20 |
| 6671842 | Asynchronous bist for embedded multiport memories | Tuan Phan, Thompson W. Crosby | 2003-12-30 |
| 6574762 | Use of a scan chain for configuration of BIST unit operation | Farzin Karimi, Thompson W. Crosby | 2003-06-03 |
| 6550032 | Detecting interport faults in multiport static memories | Jun Zhao, Mukesh K. Puri | 2003-04-15 |
| 6496950 | Testing content addressable static memories | Jun Zhao, Mukesh K. Puri | 2002-12-17 |
| 6367042 | Testing methodology for embedded memories using built-in self repair and identification circuitry | Tuan Phan | 2002-04-02 |
| 6255836 | Built-in self-test unit having a reconfigurable data retention test | William Schwarz | 2001-07-03 |
| 6101458 | Automatic ranging apparatus and method for precise integrated circuit current measurements | Emery Sugasawara, Sudhakar R. Gouravaram | 2000-08-08 |
| 6067262 | Redundancy analysis for embedded memories with built-in self test and built-in self repair | Tuan Phan, William Schwarz | 2000-05-23 |
| 6061814 | Test circuitry for determining the defect density of a semiconductor process as a function of individual metal layers | Emery Sugasawara | 2000-05-09 |
| 5987632 | Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations | Thomas R. Wik | 1999-11-16 |
| 5982659 | Memory cell capable of storing more than two logic states by using different via resistances | Thomas R. Wik, Raymond Leung, Ashok K. Kapoor, Alex Owens | 1999-11-09 |
| 5956350 | Built in self repair for DRAMs using on-chip temperature sensing and heating | Yervant David Lepejian | 1999-09-21 |
| 5867423 | Memory circuit and method for multivalued logic storage by process variations | Ashok K. Kapoor, Alex Owens, Thomas R. Wik, Raymond Leung | 1999-02-02 |
| 5847990 | Ram cell capable of storing 3 logic states | Ashok K. Kapoor, Raymond Leung, Alex Owens, Thomas R. Wik | 1998-12-08 |
| 5822228 | Method for using built in self test to characterize input-to-output delay time of embedded cores and other integrated circuits | Yervant David Lepejian | 1998-10-13 |
| 5808932 | Memory system which enables storage and retrieval of more than two states in a memory cell | Ashok K. Kapoor, Raymond Leung, Alex Owens, Thomas R. Wik | 1998-09-15 |
| 5784328 | Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array | Ashok K. Kapoor, Raymond Leung, Alex Owens, Thomas R. Wik | 1998-07-21 |
| 5761110 | Memory cell capable of storing more than two logic states by using programmable resistances | Ashok K. Kapoor, Raymond Leung, Alex Owens, Thomas R. Wik | 1998-06-02 |