Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7174341 | Dynamic database management system and method | Hovhannes Ghukasyan, Suren Chilingaryan | 2007-02-06 |
| 6966049 | Software development tool employing workflows for developing user interactive programs | Gurgen Lachinian, Hovhannes Ghukasyan, Arman Sagatelian | 2005-11-15 |
| 6920596 | Method and apparatus for determining fault sources for device failures | Arman Sagatelian, Alvin Jee, Julie Segal, John Caywood | 2005-07-19 |
| 6092030 | Timing delay generator and method including compensation for environmental variation | Lawrence Kraus, Julie Segal, John Caywood | 2000-07-18 |
| 6085346 | Method and apparatus for built-in self test of integrated circuits | Hrant Marandjian, Hovhannes Ghukasyan, Lawrence Kraus | 2000-07-04 |
| 6011748 | Method and apparatus for built-in self test of integrated circuits providing for separate row and column addresses | Hovhannes Ghukasyan, Lawrence Kraus | 2000-01-04 |
| 5983009 | Automatic generation of user definable memory BIST circuitry | Hovhannes Ghukasyan, Lawrence Kraus | 1999-11-09 |
| 5974579 | Efficient built-in self test for embedded memories with differing address spaces | Hrant Marandjian, Hovhannes Ghukasyan, John Caywood, Lawrence Kraus | 1999-10-26 |
| 5956350 | Built in self repair for DRAMs using on-chip temperature sensing and heating | V. Swamy Irrinki | 1999-09-21 |
| 5930814 | Computer system and method for synthesizing a filter circuit for filtering out addresses greater than a maximum address | Hrant Marandjian, Hovhannes Ghukasyan, Lawrence Kraus | 1999-07-27 |
| 5822228 | Method for using built in self test to characterize input-to-output delay time of embedded cores and other integrated circuits | V. Swamy Irrinki | 1998-10-13 |
| 5475695 | Automatic failure analysis system | John Caywood, Alan B. Helffrich, III | 1995-12-12 |