Issued Patents All Time
Showing 126–150 of 244 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11792998 | Process integration flow for embedded memory with multi-pocket masks for decoupling processing of memory areas from non-memory areas | Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Amrita Mathuriya, Sasikanth Manipatruni | 2023-10-17 |
| 11790969 | Apparatus and method for endurance of non-volatile memory banks via outlier compensation | Christopher B. Wilkerson, Sasikanth Manipatruni, Amrita Mathuriya | 2023-10-17 |
| 11790972 | Writing scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches and control on the plate-lines of the bit-cell | Amrita Mathuriya, Sasikanth Manipatruni | 2023-10-17 |
| 11791233 | Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging | Amrita Mathuriya, Christopher B. Wilkerson, Debo Olaosebikan, Sasikanth Manipatruni | 2023-10-17 |
| 11792997 | Common mode compensation for differential multi-element non-linear polar material based gain memory bit-cell | Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni | 2023-10-17 |
| 11784164 | 3D stacked compute and memory with copper-to-copper hybrid bond | Sasikanth Manipatruni, Amrita Mathuriya, Debo Olaosebikan | 2023-10-10 |
| 11785782 | Embedded memory with encapsulation layer adjacent to a memory stack | Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Amrita Mathuriya, Sasikanth Manipatruni | 2023-10-10 |
| 11777504 | Non-linear polar material based latch | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Sasikanth Manipatruni | 2023-10-03 |
| 11769543 | Writing scheme for 1TNC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches and control on the plate-lines of the bit-cell | Amrita Mathuriya, Sasikanth Manipatruni | 2023-09-26 |
| 11769790 | Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based trench capacitors | Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren +8 more | 2023-09-26 |
| 11770936 | Stack of planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell | Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni | 2023-09-26 |
| 11764790 | Majority logic gate having paraelectric input capacitors coupled to a conditioning scheme | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Robert Menezes, Ramamoorthy Ramesh +1 more | 2023-09-19 |
| 11764190 | 3D stacked compute and memory with copper pillars | Sasikanth Manipatruni, Amrita Mathuriya, Ramamoorthy Ramesh | 2023-09-19 |
| 11765908 | Memory device fabrication through wafer bonding | Mauricio Manfrini, Noriyuki Sato, James David Clarkson, Abel Fernandez, Somilkumar J. Rathi +4 more | 2023-09-19 |
| 11765909 | Process integration flow for embedded memory enabled by decoupling processing of a memory area from a non-memory area | Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Amrita Mathuriya, Sasikanth Manipatruni | 2023-09-19 |
| 11757452 | OR-and-invert logic based on a mix of majority or minority logic gate with non-linear input capacitors and other logic gates | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Sasikanth Manipatruni | 2023-09-12 |
| 11758738 | Integration of ferroelectric memory devices with transistors | Sasikanth Manipatruni, Ramamoorthy Ramesh, Gaurav Thareja, Amrita Mathuriya | 2023-09-12 |
| 11758708 | Stack of non-planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell | Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni | 2023-09-12 |
| 11750197 | AND-OR-invert logic based on a mix of majority OR minority logic gate with non-linear input capacitors and other logic gates | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Sasikanth Manipatruni | 2023-09-05 |
| 11751403 | Common mode compensation for 2T1C non-linear polar material based memory bit-cell | Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni | 2023-09-05 |
| 11748537 | Computer-aided design tool for logic synthesis of a mix of CMOS gates and majority and minority logic circuits | Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Amrita Mathuriya | 2023-09-05 |
| 11741428 | Iterative monetization of process development of non-linear polar material and devices | Sasikanth Manipatruni, Niloy Mukherjee, Noriyuki Sato, Tanay Gosavi, Somilkumar J. Rathi +3 more | 2023-08-29 |
| 11742860 | Fabrication of a majority logic gate having non-linear input capacitors | Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes +2 more | 2023-08-29 |
| 11735245 | Read scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects | Amrita Mathuriya, Sasikanth Manipatruni | 2023-08-22 |
| 11737283 | Method of forming a stack of non-planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell | Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni | 2023-08-22 |