Issued Patents All Time
Showing 151–175 of 244 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11729991 | Common mode compensation for non-linear polar material based differential memory bit-cell | Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni | 2023-08-15 |
| 11729995 | Common mode compensation for non-linear polar material 1TnC memory bit-cell | Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni | 2023-08-15 |
| 11721690 | Method of adjusting threshold of a ferroelectric capacitive-input circuit | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Sasikanth Manipatruni | 2023-08-08 |
| 11716086 | Asynchronous circuit with majority gate or minority gate logic and 1-input threshold gate | Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Amrita Mathuriya | 2023-08-01 |
| 11716085 | Pull-up and pull-down networks controlled asynchronously by threshold gate logic | Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Amrita Mathuriya | 2023-08-01 |
| 11716084 | Pull-up and pull-down networks controlled asynchronously by majority gate or minority gate logic | Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Amrita Mathuriya | 2023-08-01 |
| 11716083 | Asynchronous circuit with threshold logic | Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Amrita Mathuriya | 2023-08-01 |
| 11711083 | Majority gate based low power ferroelectric based adder with reset mechanism | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Guarav Thareja, Ramamoorthy Ramesh +1 more | 2023-07-25 |
| 11705906 | Majority logic gate having ferroelectric input capacitors and a pulsing scheme coupled to a conditioning logic | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Robert Menezes, Ramamoorthy Ramesh +1 more | 2023-07-18 |
| 11705905 | Multi-function ferroelectric threshold gate with input based adaptive threshold | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Sasikanth Manipatruni | 2023-07-18 |
| 11699699 | Multi-function threshold gate with adaptive threshold and stacked planar ferroelectric capacitors | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Debo Olaosebikan, Sasikanth Manipatruni | 2023-07-11 |
| 11696451 | Common mode compensation for non-linear polar material based 1T1C memory bit-cell | Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni | 2023-07-04 |
| 11696450 | Common mode compensation for multi-element non-linear polar material based gain memory bit-cell | Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni | 2023-07-04 |
| 11694940 | 3D stack of accelerator die and multi-core processor die | Amrita Mathuriya, Christopher B. Wilkerson, Debo Olaosebikan, Sasikanth Manipatruni | 2023-07-04 |
| 11694737 | Write scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize write disturb effects | Amrita Mathuriya, Sasikanth Manipatruni | 2023-07-04 |
| 11688733 | Method of adjusting threshold of a paraelectric capacitive-input circuit | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Sasikanth Manipatruni | 2023-06-27 |
| 11670352 | Apparatus and method for endurance of non-volatile memory banks via wear leveling and outlier compensation | Christopher B. Wilkerson, Sasikanth Manipatruni, Amrita Mathuriya | 2023-06-06 |
| 11664060 | Writing scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell | Amrita Mathuriya, Sasikanth Manipatruni | 2023-05-30 |
| 11664371 | Multi-function threshold gate with adaptive threshold and stacked planar paraelectric capacitors | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Debo Olaosebikan, Sasikanth Manipatruni | 2023-05-30 |
| 11664370 | Multi-function paraelectric threshold gate with input based adaptive threshold | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Sasikanth Manipatruni | 2023-05-30 |
| 11658664 | Asynchronous circuit with majority gate or minority gate logic | Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Amrita Mathuriya | 2023-05-23 |
| 11652487 | Parallel pull-up and pull-down networks controlled asynchronously by majority gate or minority gate logic | Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Amrita Mathuriya | 2023-05-16 |
| 11652482 | Parallel pull-up and pull-down networks controlled asynchronously by threshold logic gate | Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Amrita Mathuriya | 2023-05-16 |
| 11646071 | Reading scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches and control on plate-lines of the bit-cell | Amrita Mathuriya, Sasikanth Manipatruni | 2023-05-09 |
| 11641205 | Reset mechanism for a chain of majority or minority gates having paraelectric material | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Sasikanth Manipatruni | 2023-05-02 |