Issued Patents All Time
Showing 201–225 of 244 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11501813 | Method of forming stacked ferroelectric non- planar capacitors in a memory bit-cell | Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan, Amrita Mathuriya +1 more | 2022-11-15 |
| 11502691 | Method for using and forming low power ferroelectric based majority logic gate adder | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Gaurav Thareja, Ramamoorthy Ramesh +1 more | 2022-11-15 |
| 11482270 | Pulsing scheme for a ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic | Amrita Mathuriya, Sasikanth Manipatruni | 2022-10-25 |
| 11482529 | High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor | Sasikanth Manipatruni, Ramamoorthy Ramesh | 2022-10-25 |
| 11482990 | Vectored sequential circuit with ferroelectric or paraelectric material | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Sasikanth Manipatruni | 2022-10-25 |
| 11482528 | Pillar capacitor and method of fabricating such | Gaurav Thareja, Sasikanth Manipatruni, Ramamoorthy Ramesh, Amrita Mathuriya | 2022-10-25 |
| 11476260 | High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor | Sasikanth Manipatruni, Ramamoorthy Ramesh | 2022-10-18 |
| 11476261 | High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor | Sasikanth Manipatruni, Ramamoorthy Ramesh | 2022-10-18 |
| 11451232 | Majority logic gate based flip-flop with non-linear polar material | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Ramamoorthy Ramesh, Amrita Mathuriya | 2022-09-20 |
| 11430861 | Ferroelectric capacitor and method of patterning such | Gaurav Thareja, Sasikanth Manipatruni, Ramamoorthy Ramesh, Amrita Mathuriya | 2022-08-30 |
| 11423967 | Stacked ferroelectric non-planar capacitors in a memory bit-cell | Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan, Amrita Mathuriya +1 more | 2022-08-23 |
| 11418197 | Majority logic gate having paraelectric input capacitors and a local conditioning mechanism | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Robert Menezes, Ramamoorthy Ramesh +1 more | 2022-08-16 |
| 11394387 | 2-input NAND gate with non-linear input capacitors | Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes +2 more | 2022-07-19 |
| 11381244 | Low power ferroelectric based majority logic gate multiplier | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Gaurav Thareja, Ramamoorthy Ramesh +1 more | 2022-07-05 |
| 11374575 | Majority logic gate with non-linear input capacitors and conditioning logic | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Robert Menezes, Ramamoorthy Ramesh +1 more | 2022-06-28 |
| 11373727 | Apparatus for improving memory bandwidth through read and restore decoupling | Christopher B. Wilkerson, Sasikanth Manipatruni, Amrita Mathuriya | 2022-06-28 |
| 11373728 | Method for improving memory bandwidth through read and restore decoupling | Christopher B. Wilkerson, Sasikanth Manipatruni, Amrita Mathuriya | 2022-06-28 |
| 11374574 | Linear input and non-linear output threshold logic gate | Sasikanth Manipatruni, Robert Menezes, Yuan-Sheng Fang, Gaurav Thareja, Ramamoorthy Ramesh +1 more | 2022-06-28 |
| 11366589 | Efficient method for improving memory bandwidth through read and restore decoupling using restore buffer | Christopher B. Wilkerson, Sasikanth Manipatruni, Amrita Mathuriya | 2022-06-21 |
| 11303280 | Ferroelectric or paraelectric based sequential circuit | Amrita Mathuriya, Ikenna Odinaka, Rafael Rios, Sasikanth Manipatruni | 2022-04-12 |
| 11296708 | Low power ferroelectric based majority logic gate adder | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Gaurav Thareja, Ramamoorthy Ramesh +1 more | 2022-04-05 |
| 11295796 | Apparatus and method for endurance of non-volatile memory banks via wear leveling and random swap injection | Christopher B. Wilkerson, Sasikanth Manipatruni, Amrita Mathuriya | 2022-04-05 |
| 11289497 | Integration method of ferroelectric memory array | Gaurav Thareja, Sasikanth Manipatruni, Ramamoorthy Ramesh, Amrita Mathuriya | 2022-03-29 |
| 11290111 | Majority logic gate based and-or-invert logic gate with non-linear input capacitors | Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes +2 more | 2022-03-29 |
| 11290112 | Majority logic gate based XOR logic gate with non-linear input capacitors | Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes +2 more | 2022-03-29 |