Issued Patents All Time
Showing 176–200 of 258 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11658664 | Asynchronous circuit with majority gate or minority gate logic | Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania | 2023-05-23 |
| 11652487 | Parallel pull-up and pull-down networks controlled asynchronously by majority gate or minority gate logic | Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania | 2023-05-16 |
| 11652482 | Parallel pull-up and pull-down networks controlled asynchronously by threshold logic gate | Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania | 2023-05-16 |
| 11646071 | Reading scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches and control on plate-lines of the bit-cell | Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-05-09 |
| 11641205 | Reset mechanism for a chain of majority or minority gates having paraelectric material | Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-05-02 |
| 11641747 | Integration of a ferroelectric memory device with a transistor | Gaurav Thareja, Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh | 2023-05-02 |
| 11637090 | Method of forming a 3D stacked compute and memory | Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh | 2023-04-25 |
| 11616507 | Ferroelectric based latch | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh | 2023-03-28 |
| 11610620 | Pulsing scheme for a 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line to minimize read or write disturb effects | Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-03-21 |
| 11610619 | Pulsing scheme for a 1TNC ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects | Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-03-21 |
| 11611345 | NAND based sequential circuit with ferroelectric or paraelectric material | Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni | 2023-03-21 |
| 11605411 | Method of forming stacked ferroelectric planar capacitors in a memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan +1 more | 2023-03-14 |
| 11605413 | Reading scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell | Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-03-14 |
| 11545204 | Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan +1 more | 2023-01-03 |
| 11545979 | Compare logic based sequential circuit with ferroelectric or paraelectric material | Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni | 2023-01-03 |
| 11538514 | Writing scheme for 1TnC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell | Rajeev Kumar Dokania, Sasikanth Manipatruni | 2022-12-27 |
| 11539368 | Majority logic gate with input paraelectric capacitors | Sasikanth Manipatruni, Rafael Rios, Ikenna Odinaka, Robert Menezes, Rajeev Kumar Dokania +1 more | 2022-12-27 |
| 11532635 | High-density low voltage multi-element ferroelectric gain memory bit-cell with pillar capacitors | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan +1 more | 2022-12-20 |
| 11532342 | Non-linear polar material based differential multi-memory element bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan +1 more | 2022-12-20 |
| 11532344 | Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches on plate-lines of the bit-cell | Rajeev Kumar Dokania, Sasikanth Manipatruni | 2022-12-20 |
| 11527278 | Non-linear polar material based memory bit-cell with multi-level storage by applying different time pulse widths | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan +1 more | 2022-12-13 |
| 11527277 | High-density low voltage ferroelectric memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan +1 more | 2022-12-13 |
| 11522044 | Ferroelectric capacitor integrated with logic | Gaurav Thareja, Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh | 2022-12-06 |
| 11521666 | High-density low voltage multi-element ferroelectric gain memory bit-cell with planar capacitors | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan +1 more | 2022-12-06 |
| 11521667 | Stacked ferroelectric planar capacitors in a memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan +1 more | 2022-12-06 |