Issued Patents All Time
Showing 151–175 of 258 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11741428 | Iterative monetization of process development of non-linear polar material and devices | Sasikanth Manipatruni, Niloy Mukherjee, Noriyuki Sato, Tanay Gosavi, Somilkumar J. Rathi +3 more | 2023-08-29 |
| 11742860 | Fabrication of a majority logic gate having non-linear input capacitors | Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes +2 more | 2023-08-29 |
| 11737283 | Method of forming a stack of non-planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Sasikanth Manipatruni | 2023-08-22 |
| 11735245 | Read scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects | Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-08-22 |
| 11729995 | Common mode compensation for non-linear polar material 1TnC memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Sasikanth Manipatruni | 2023-08-15 |
| 11729991 | Common mode compensation for non-linear polar material based differential memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Sasikanth Manipatruni | 2023-08-15 |
| 11727260 | Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits | Abhishek A. Sharma, Jack T. Kavalieros, Ian A. Young, Ram Krishnamurthy, Sasikanth Manipatruni +7 more | 2023-08-15 |
| 11721690 | Method of adjusting threshold of a ferroelectric capacitive-input circuit | Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-08-08 |
| 11716086 | Asynchronous circuit with majority gate or minority gate logic and 1-input threshold gate | Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania | 2023-08-01 |
| 11716085 | Pull-up and pull-down networks controlled asynchronously by threshold gate logic | Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania | 2023-08-01 |
| 11716084 | Pull-up and pull-down networks controlled asynchronously by majority gate or minority gate logic | Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania | 2023-08-01 |
| 11716083 | Asynchronous circuit with threshold logic | Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania | 2023-08-01 |
| 11711083 | Majority gate based low power ferroelectric based adder with reset mechanism | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Guarav Thareja +1 more | 2023-07-25 |
| 11705906 | Majority logic gate having ferroelectric input capacitors and a pulsing scheme coupled to a conditioning logic | Rajeev Kumar Dokania, Rafael Rios, Ikenna Odinaka, Robert Menezes, Ramamoorthy Ramesh +1 more | 2023-07-18 |
| 11705905 | Multi-function ferroelectric threshold gate with input based adaptive threshold | Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-07-18 |
| 11699699 | Multi-function threshold gate with adaptive threshold and stacked planar ferroelectric capacitors | Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2023-07-11 |
| 11696451 | Common mode compensation for non-linear polar material based 1T1C memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Sasikanth Manipatruni | 2023-07-04 |
| 11696450 | Common mode compensation for multi-element non-linear polar material based gain memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Sasikanth Manipatruni | 2023-07-04 |
| 11694940 | 3D stack of accelerator die and multi-core processor die | Christopher B. Wilkerson, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2023-07-04 |
| 11694737 | Write scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize write disturb effects | Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-07-04 |
| 11688733 | Method of adjusting threshold of a paraelectric capacitive-input circuit | Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-06-27 |
| 11670352 | Apparatus and method for endurance of non-volatile memory banks via wear leveling and outlier compensation | Christopher B. Wilkerson, Sasikanth Manipatruni, Rajeev Kumar Dokania | 2023-06-06 |
| 11664060 | Writing scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell | Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-05-30 |
| 11664371 | Multi-function threshold gate with adaptive threshold and stacked planar paraelectric capacitors | Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2023-05-30 |
| 11664370 | Multi-function paraelectric threshold gate with input based adaptive threshold | Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2023-05-30 |