Issued Patents All Time
Showing 51–62 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8709935 | Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties | DaeSik Choi, OhHan Kim | 2014-04-29 |
| 8574964 | Semiconductor device and method of forming electrical interconnection between semiconductor die and substrate with continuous body of solder tape | Taewoo Lee, DaeSik Choi, KyuWon Lee | 2013-11-05 |
| 8519544 | Semiconductor device and method of forming WLCSP structure using protruded MLP | OhHan Kim, DaeSik Choi, KyuWon Lee, DongSoo Moo | 2013-08-27 |
| 8502387 | Integrated circuit packaging system with vertical interconnection and method of manufacture thereof | DaeSik Choi, Taewoo Lee, KyuWon Lee | 2013-08-06 |
| 8502391 | Semiconductor device and method of making single layer substrate with asymmetrical fibers and reduced warpage | Hyung Sang Park, Sung-Soo Kim | 2013-08-06 |
| 8492197 | Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate | KiYoun Jang, YongHee Kang, Hyung Sang Park | 2013-07-23 |
| 8461680 | Integrated circuit packaging system with rounded interconnect | JoHyun Bae, DaeSik Choi | 2013-06-11 |
| 8409979 | Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties | DaeSik Choi, OhHan Kim | 2013-04-02 |
| 8288203 | Semiconductor device and method of forming a wafer level package structure using conductive via and exposed bump | JoonYoung Choi, DaeSik Choi | 2012-10-16 |
| 8273604 | Semiconductor device and method of forming WLCSP structure using protruded MLP | OhHan Kim, DaeSik Choi, KyuWon Lee, DongSoo Moo | 2012-09-25 |
| 8173536 | Semiconductor device and method of forming column interconnect structure to reduce wafer stress | TaeWoo Kang | 2012-05-08 |
| 8039275 | Integrated circuit packaging system with rounded interconnect and method of manufacture thereof | JoHyun Bae, DaeSik Choi | 2011-10-18 |