TW

Tobias Werner

IBM: 32 patents #3,111 of 70,183Top 5%
Robert Bosch Gmbh: 4 patents #4,370 of 19,740Top 25%
Overall (All Time): #93,785 of 4,157,543Top 3%
36
Patents All Time

Issued Patents All Time

Showing 25 most recent of 36 patents

Patent #TitleCo-InventorsDate
11467078 Laser-induced incandescent particle sensor comprising a confocal arrangement of a laser spot and of a thermal radiation spot Jens Ehlermann, Matthias Wichmann, Radoslav Rusanov 2022-10-11
11328110 Integrated circuit including logic circuitry Juergen Pille, Shankar Kalyanasundaram, Rolf Sautter 2022-05-10
11171142 Integrated circuit with vertical structures on nodes of a grid Juergen Pille, Albert Frisch, Rolf Sautter, Dieter Wendel 2021-11-09
11164879 Microelectronic device with a memory element utilizing stacked vertical devices Juergen Pille, Albert Frisch, Rolf Sautter, Dieter Wendel 2021-11-02
10833089 Buried conductive layer supplying digital circuits Juergen Pille, Albert Frisch, Rolf Sautter, Dieter Wendel 2020-11-10
10804266 Microelectronic device utilizing stacked vertical devices Juergen Pille, Albert Frisch, Rolf Sautter, Dieter Wendel 2020-10-13
10712568 Projection device for data eyeglasses, data eyeglasses, and method for operating a projection device for data eyeglasses Reinhold Fiess 2020-07-14
10565340 Field-effect transistor placement optimization for improved leaf cell routability Iris Maria Leefken, Silke Penth, Michael Stetter 2020-02-18
10394994 Field-effect transistor placement optimization for improved leaf cell routability Iris Maria Leefken, Silke Penth, Michael Stetter 2019-08-27
9997218 Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation Paul A. Bunce, Yuen H. Chan, John D. Davis, Silke Penth, David Edward Schmitt +1 more 2018-06-12
9904754 Layout of interconnect lines in integrated circuits Gerhard Hellner, Iris Maria Leefken, Silke Penth 2018-02-27
9898571 Layout of interconnect lines in integrated circuits Gerhard Hellner, Iris Maria Leefken, Silke Penth 2018-02-20
9837142 Automated stressing and testing of semiconductor memory cells Yuen H. Chan, Michael Kugel, Stefan Payer, Wolfgang Penth, Juergen Pille 2017-12-05
9805823 Automated stressing and testing of semiconductor memory cells Yuen H. Chan, Michael Kugel, Stefan Payer, Wolfgang Penth, Juergen Pille 2017-10-31
9792967 Managing semiconductor memory array leakage current Paul A. Bunce, Yuen H. Chan, John D. Davis, Silke Penth, David Edward Schmitt +1 more 2017-10-17
9786339 Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation Paul A. Bunce, Yuen H. Chan, John D. Davis, Silke Penth, David Edward Schmitt +1 more 2017-10-10
9761289 Managing semiconductor memory array leakage current Paul A. Bunce, Yuen H. Chan, John D. Davis, Silke Penth, David Edward Schmitt +1 more 2017-09-12
9711244 Memory circuit Yuen H. Chan, Silke Penth, David Edward Schmitt 2017-07-18
9627017 RAM at speed flexible timing and setup control Martin Eckert, Michael Kugel, Otto A. Torreiter 2017-04-18
9627090 RAM at speed flexible timing and setup control Martin Eckert, Michael Kugel, Otto A. Torreiter 2017-04-18
9537474 Transforming a phase-locked-loop generated chip clock signal to a local clock signal Yuen H. Chan, Juergen Pille, Rolf Sautter 2017-01-03
9437285 Write address synchronization in 2 read/1write SRAM arrays Harry Barowski, Silke Penth, Wolfgang Penth 2016-09-06
9406375 Write address synchronization in 2 read/1write SRAM arrays Harry Barowski, Silke Penth, Wolfgang Penth 2016-08-02
9401597 Method and device for discharging an intermediate circuit of a power supply network Stefan Mangold 2016-07-26
9401698 Transforming a phase-locked-loop generated chip clock signal to a local clock signal Yuen H. Chan, Juergen Pille, Rolf Sautter 2016-07-26