Issued Patents All Time
Showing 25 most recent of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12118057 | Computing partial matrices at hardware accelerator | Derek Gladding, Nitin N. Garegrat, Balamurugan Kulanthivelu Veluchamy | 2024-10-15 |
| 11768714 | On-chip hardware semaphore array supporting multiple conditionals | Xiaoling Xu, Deepak Goel | 2023-09-26 |
| 11176448 | Enhancing processing performance of a DNN module by bandwidth control of fabric interface | Chad B. McBride, Amol Ashok Ambardekar, George Petre, Kent D. Cedola, Larry Marvin Wall +1 more | 2021-11-16 |
| 10862509 | Flexible huffman tree approximation for low latency encoding | Bogdan Alexandru Burlacu | 2020-12-08 |
| 10628345 | Enhancing processing performance of a DNN module by bandwidth control of fabric interface | Chad B. McBride, Amol Ashok Ambardekar, George Petre, Kent D. Cedola, Larry Marvin Wall +1 more | 2020-04-21 |
| 9921846 | Global branch prediction using branch and fetch group history | Andrew D. Hilton | 2018-03-20 |
| 9858081 | Global branch prediction using branch and fetch group history | Andrew D. Hilton | 2018-01-02 |
| 9733943 | Branch history cache and method | Brent F. Hilgart, Andrew D. Hilton | 2017-08-15 |
| 9262160 | Load latency speculation in an out-of-order computer processor | Andrew D. Hilton, Adam J. Muff | 2016-02-16 |
| 9256428 | Load latency speculation in an out-of-order computer processor | Andrew D. Hilton, Adam J. Muff | 2016-02-09 |
| 8983891 | Pattern matching engine for use in a pattern matching accelerator | Giora Biran, Christoph Hagleitner, Russell D. Hoover, Jan Van Lunteren | 2015-03-17 |
| 8966182 | Software and hardware managed dual rule bank cache for use in a pattern matching accelerator | Giora Biran, Christoph Hagleitner, Russell D. Hoover, Jan Van Lunteren | 2015-02-24 |
| 8843706 | Memory management among levels of cache in a memory hierarchy | Robert A. Shearer | 2014-09-23 |
| 8799188 | Algorithm engine for use in a pattern matching accelerator | Giora Biran, Christoph Hagleitner, Russell D. Hoover, Jan Van Lunteren | 2014-08-05 |
| 8635180 | Multiple hash scheme for use in a pattern matching accelerator | Giora Biran, Christoph Hagleitner, Jan Van Lunteren | 2014-01-21 |
| 8572325 | Dynamic adjustment of read/write ratio of a disk cache | Ganesh Balakrishnan, Gordon B. Bell, MVV Anil Krishna, Brian M. Rogers | 2013-10-29 |
| 8495334 | Address translation for use in a pattern matching accelerator | Giora Biran, Christoph Hagleitner, Jan Van Lunteren | 2013-07-23 |
| 8478736 | Pattern matching accelerator | Giora Biran, Christoph Hagleitner, Russell D. Hoover, Jan Van Lunteren | 2013-07-02 |
| 8447749 | Local results processor for use in a pattern matching accelerator | Giora Biran, Christoph Hagleitner, Jan Van Lunteren | 2013-05-21 |
| 8423715 | Memory management among levels of cache in a memory hierarchy | Robert A. Shearer | 2013-04-16 |
| 8423533 | Multiple rule bank access scheme for use in a pattern matching accelerator | Giora Biran, Christoph Hagleitner, Jan Van Lunteren | 2013-04-16 |
| 8412722 | Upload manager for use in a pattern matching accelerator | Giora Biran, Christoph Hagleitner, Uzi Shvadron, Jan Van Lunteren | 2013-04-02 |
| 8402003 | Performance monitoring mechanism for use in a pattern matching accelerator | Giora Biran, Christoph Hagleitner, Jan Van Lunteren | 2013-03-19 |
| 8296547 | Loading entries into a TLB in hardware via indirect TLB entries | Benjamin Herrenschmidt, Jon K. Kriegel, Paul Mackerras, Andrew Henry Wottreng | 2012-10-23 |
| 8255887 | Method and apparatus for re-using memory allocated for data structures used by software processes | — | 2012-08-28 |