Issued Patents All Time
Showing 1–25 of 235 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431877 | Hybrid flop tray including different fin size flip-flops | Ramaprasath Vilangudipitchai, Rui-Hua Chen, Venugopal Boynapalli | 2025-09-30 |
| 11823052 | Configurable MAC for neural network applications | Giby Samson, Srivatsan Chellappa, Ramaprasath Vilangudipitchai | 2023-11-21 |
| 11710733 | Vertical power grid standard cell architecture | Hyeokjin Lim, Bharani Chava, Foua Vang, Venugopal Boynapalli | 2023-07-25 |
| 11476186 | MIMCAP architecture | Ramaprasath Vilangudipitchai, Gudoor Reddy, Samrat Sinharoy, Smeeta Heggond, Anil Kumar KODURU +1 more | 2022-10-18 |
| 11437379 | Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits | Stanley Seungchul Song, Deepak Sharma, Bharani Chava, Hyeokjin Lim, Peijie Feng +6 more | 2022-09-06 |
| 11404374 | Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods | Hyeokjin Lim, Stanley Seungchul Song, Foua Vang | 2022-08-02 |
| 11290109 | Multibit multi-height cell to improve pin accessibility | Foua Vang, Hyeokjin Lim, Venugopal Boynapalli, Shitiz Arora | 2022-03-29 |
| 11237580 | Systems and methods providing leakage reduction for power gated domains | Giby Samson, Foua Vang, Ramaprasath Vilangudipitchai, Venugopal Boynapalli | 2022-02-01 |
| 10868238 | Magnetic tunnel junction integration without patterning process | Xia Li, Wei-Chuan Chen | 2020-12-15 |
| 10833254 | Engineered barrier layer interface for high speed spin-transfer torque magnetic random access memory | Chando Park, Jimmy Jianan Kan, Peiyuan Wang | 2020-11-10 |
| 10811068 | Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications | Xia Li, Wei-Chuan Chen, Wah Nam Hsu | 2020-10-20 |
| 10803942 | Transistor noise tolerant, non-volatile (NV) resistance element-based static random access memory (SRAM) physically unclonable function (PUF) circuits, and related systems and methods | Seong-Ook Jung, Byungkyu Song, Sehee Lim, Sungryul Kim | 2020-10-13 |
| 10740017 | Dynamic memory protection | Chando Park, Wei-Chuan Chen, Sungryul Kim, Adam E. Newham, Rashid Ahmed Akbar Attar | 2020-08-11 |
| 10636962 | Spin-orbit torque (SOT) magnetic tunnel junction (MTJ) (SOT-MTJ) devices employing perpendicular and in-plane free layer magnetic anisotropy to facilitate perpendicular magnetic orientation switching, suitable for use in memory systems for storing data | Chando Park, Sungryul Kim | 2020-04-28 |
| 10615988 | Compact and reliable physical unclonable function devices and methods | Xia Li, Bin Yang, Gengming Tao | 2020-04-07 |
| 10547460 | Message-based key generation using physical unclonable function (PUF) | Peiyuan Wang, Chando Park, Jimmy Jianan Kan | 2020-01-28 |
| 10534047 | Tunnel magneto-resistive (TMR) sensors employing TMR devices with different magnetic field sensitivities for increased detection sensitivity | Wei-Chuan Chen, Wah Nam Hsu, Xia Li, Nicholas Ka Ming Stevens-Yu | 2020-01-14 |
| 10483457 | Differential spin orbit torque magnetic random access memory (SOT-MRAM) cell structure and array | Hochul Lee, Chando Park | 2019-11-19 |
| 10460785 | Parallel write scheme utilizing spin hall effect-assisted spin transfer torque random access memory | Hochul Lee, Chando Park | 2019-10-29 |
| 10460817 | Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors | Xia Li, Wei-Chuan Chen | 2019-10-29 |
| 10460780 | Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory | Sungryul Kim, Chando Park | 2019-10-29 |
| 10431278 | Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature | Xia Li, Wah Nam Hsu, Wei-Chuan Chen | 2019-10-01 |
| 10431734 | Engineered barrier layer interface for high speed spin-transfer torque magnetic random access memory | Chando Park, Jimmy Jianan Kan, Peiyuan Wang | 2019-10-01 |
| 10424380 | Physically unclonable function (PUF) memory employing static random access memory (SRAM) bit cells with added passive resistance to enhance transistor imbalance for improved PUF output reproducibility | Xia Li, Jianguo Yao | 2019-09-24 |
| 10410714 | Multi-level cell (MLC) static random access memory (SRAM) (MLC SRAM) cells configured to perform multiplication operations | Xia Li, Venkat Rangan, Rashid Ahmed Akbar Attar, Nicholas Ka Ming Stevens-Yu | 2019-09-10 |