Issued Patents All Time
Showing 25 most recent of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11663151 | Network-on-chip for neurological data | Dongjin Seo, Manuel Alejandro Monge Osorio | 2023-05-30 |
| 11630516 | Brain-machine interface (BMI) with user interface (UI) aware controller | Nir Even Chen, Joseph O'Doherty | 2023-04-18 |
| 11580366 | Neuromorphic event-driven neural computing architecture in a scalable neural network | Filipp A. Akopyan, John V. Arthur, Rajit Manohar, Dharmendra S. Modha, Alyosha Molnar +1 more | 2023-02-14 |
| 11341401 | Hardware architecture for simulating a neural network of neurons | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Dharmendra S. Modha | 2022-05-24 |
| 11295201 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network | John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Dharmendra S. Modha +3 more | 2022-04-05 |
| 11238343 | Scalable neural hardware for the noisy-OR model of Bayesian networks | John V. Arthur, Steven K. Esser, Dharmendra S. Modha | 2022-02-01 |
| 11216400 | Network-on-chip for neurological data | Dongjin Seo, Manuel Alejandro Monge Osorio | 2022-01-04 |
| 11184221 | Yield tolerance in a neurosynaptic system | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Dharmendra S. Modha +1 more | 2021-11-23 |
| 11074496 | Providing transposable access to a synapse array using a recursive array layout | John V. Arthur, John E. Barth, Jr., Dharmendra S. Modha | 2021-07-27 |
| 11049001 | Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Dharmendra S. Modha +1 more | 2021-06-29 |
| 10990872 | Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency | Filipp A. Akopyan, Rodrigo Alvarez-Icaza, John V. Arthur, Andrew S. Cassidy, Steven K. Esser +3 more | 2021-04-27 |
| 10984312 | Mapping graphs onto core-based neuromorphic architectures | Arnon Amir, Pallab Datta, Dharmendra S. Modha | 2021-04-20 |
| 10984307 | Peripheral device interconnections for neurosynaptic systems | Filipp A. Akopyan, Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson +2 more | 2021-04-20 |
| 10929747 | Dual deterministic and stochastic neurosynaptic core circuit | Rodrigo Alvarez-Icaza, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Dharmendra S. Modha +1 more | 2021-02-23 |
| 10839287 | Globally asynchronous and locally synchronous (GALS) neuromorphic network | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Dharmendra S. Modha | 2020-11-17 |
| 10838860 | Memory-mapped interface to message-passing computing systems | Filipp A. Akopyan, John V. Arthur, Andrew S. Cassidy, Michael Vincent DeBole, Dharmendra S. Modha +1 more | 2020-11-17 |
| 10832125 | Implementing a neural network algorithm on a neurosynaptic substrate based on metadata associated with the neural network algorithm | Arnon Amir, Rathinakumar Appuswamy, Pallab Datta, Myron D. Flickner, Dharmendra S. Modha +1 more | 2020-11-10 |
| 10824579 | Network-on-chip for neurological data | Dongjin Seo, Manuel Alejandro Monge Osorio | 2020-11-03 |
| 10785745 | Scaling multi-core neurosynaptic networks across chip boundaries | Rodrigo Alvarez Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Dharmendra S. Modha +1 more | 2020-09-22 |
| 10769519 | Converting digital numeric data to spike event data | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner +4 more | 2020-09-08 |
| 10755165 | Converting spike event data to digital numeric data | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner +4 more | 2020-08-25 |
| 10740282 | Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer +3 more | 2020-08-11 |
| 10713561 | Multiplexing physical neurons to optimize power and area | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Dharmendra S. Modha | 2020-07-14 |
| 10650301 | Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation | Rodrigo Alvarez-Icaza Rivera, Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson +2 more | 2020-05-12 |
| 10504021 | Neuromorphic event-driven neural computing architecture in a scalable neural network | Filipp A. Akopyan, John V. Arthur, Rajit Manohar, Dharmendra S. Modha, Alyosha Molnar +1 more | 2019-12-10 |