Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9405696 | Cache and method for cache bypass functionality | Blaine D. Gaither | 2016-08-02 |
| 8683139 | Cache and method for cache bypass functionality | Blaine D. Gaither | 2014-03-25 |
| 8505020 | Computer workload migration using processor pooling | Christophe de Dinechin, Dale Morris, Russ W. Herrell | 2013-08-06 |
| 8176255 | Allocating space in dedicated cache ways | — | 2012-05-08 |
| 8103837 | Servicing memory read requests | Matthew Lovell, Pavel Vasek | 2012-01-24 |
| 7941610 | Coherency directory updating in a multiprocessor computing system | Erin A. Handgen | 2011-05-10 |
| 7600079 | Performing a memory write of a data unit without changing ownership of the data unit | Blaine D. Gaither, Judson E. Veazey | 2009-10-06 |
| 7343479 | Method and apparatus for implementing two architectures in a chip | Kevin Safford, Donald Soltis, Joel D. Lamb, Stephen R. Undy, Russell C. Brockmann | 2008-03-11 |
| 7139936 | Method and apparatus for verifying the correctness of a processor behavioral model | Jeremy Petsinger, Kevin Safford, Karl Brummel, Russell C. Brockmann, Bruce Long | 2006-11-21 |
| 6820190 | Method and computer system for decomposing macroinstructions into microinstructions and forcing the parallel issue of at least two microinstructions | Kevin Safford | 2004-11-16 |
| 6807625 | Method and apparatus for efficiently generating, storing, and consuming arithmetic flags between producing and consuming macroinstructions when emulating with microinstructions | Mark Gibson, Rohit Bhatia, Kevin Safford | 2004-10-19 |
| 6745322 | Apparatus and method for conditionally flushing a pipeline upon a failure of a test condition | Russell C. Brockmann, Kevin Safford, Rohit Bhatia | 2004-06-01 |
| 6681322 | Method and apparatus for emulating an instruction set extension in a digital computer system | Kevin Safford | 2004-01-20 |
| 6668315 | Methods and apparatus for exchanging the contents of registers | Kevin Safford | 2003-12-23 |
| 6643800 | Method and apparatus for testing microarchitectural features by using tests written in microcode | Kevin Safford, Russell C. Brockmann, Karl Brummel, M A Susith Rohana Fernando | 2003-11-04 |
| 6625759 | Method and apparatus for verifying the fine-grained correctness of a behavioral model of a central processor unit | Jeremy Petsinger, Kevin Safford, Karl Brummel, Russell C. Brockmann, Bruce Long | 2003-09-23 |
| 6618801 | Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information | Kevin Safford, Donald Soltis, Joel D. Lamb, Stephen R. Undy, Russell C. Brockmann | 2003-09-09 |
| 6542862 | Determining register dependency in multiple architecture systems | Kevin Safford, Joel D. Lamb | 2003-04-01 |
| 6003107 | Circuitry for providing external access to signals that are internal to an integrated circuit chip package | Gregory L. Ranson, John W. Bockhaus, Gregg B. Lesartre, Paul L. Perez | 1999-12-14 |
| 5867644 | System and method for on-chip debug support and performance monitoring in a microprocessor | Gregory L. Ranson, John W. Bockhaus, Gregg B. Lesartre, Russell C. Brockmann, Robert E. Naas +4 more | 1999-02-02 |
| 5860096 | Multi-level instruction cache for a computer | Stephen R. Undy, Craig A. Gleason | 1999-01-12 |
| 5829049 | Simultaneous execution of two memory reference instructions with only one address calculation | William L. Walker, Mark R. Storey, Stephen R. Undy | 1998-10-27 |
| 5526500 | System for operand bypassing to allow a one and one-half cycle cache memory access time for sequential load and branch instructions | Darius Tanksalvala, Eric Delano, Thomas R. Hotchkiss, R. Craig Simpson | 1996-06-11 |
| 5412787 | Two-level TLB having the second level TLB implemented in cache tag RAMs | Mark A. Forsyth | 1995-05-02 |