Issued Patents All Time
Showing 1–25 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12174251 | System testing using partitioned and controlled noise | Eugene Atwood, William V. Huott, Dustin Feller | 2024-12-24 |
| 12105834 | User privacy for autonomous vehicles | Franco Motika, Eugene Atwood | 2024-10-01 |
| 11378623 | Diagnostic enhancement for multiple instances of identical structures | Steven M. Douskey, Orazio P. Forlenza, Franco Motika, Gerard M. Salem | 2022-07-05 |
| 11112457 | Dynamic weight selection process for logic built-in self test | Franco Motika, Eugene Atwood | 2021-09-07 |
| 11112854 | Operating pulsed latches on a variable power supply | Steven M. Douskey, Raghu G. GopalaKrishnaSetty, Hari Krishnan Rajeev, James D. Warnock | 2021-09-07 |
| 11079433 | Logic built-in self test dynamic weight selection method | Franco Motika, Eugene Atwood | 2021-08-03 |
| 10930364 | Iterative functional test exerciser reload and execution | Franco Motika, Gerard M. Salem | 2021-02-23 |
| 10816599 | Dynamically power noise adaptive automatic test pattern generation | Steven M. Douskey, Raghu G. GopalaKrishnaSetty, Sumit Panigrahi | 2020-10-27 |
| 10768230 | Built-in device testing of integrated circuits | Robert M. Casatuta, Gary W. Maier, Franco Motika, Phong T. Tran | 2020-09-08 |
| 10746794 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Raghu G. GopalaKrishnaSetty, Cedric Lichtenau | 2020-08-18 |
| 10739401 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Raghu G. GopalaKrishnaSetty, Cedric Lichtenau | 2020-08-11 |
| 10649028 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Raghu G. GopalaKrishnaSetty, Cedric Lichtenau | 2020-05-12 |
| 10613142 | Non-destructive recirculation test support for integrated circuits | Franco Motika, Gerard M. Salem | 2020-04-07 |
| 10598727 | Identification of unknown sources for logic built-in self test in verification | Satya R. S. Bhamidipati, Cedric Lichtenau, Srinivas V. N. Polisetty | 2020-03-24 |
| 10585142 | Functional diagnostics based on dynamic selection of alternate clocking | Franco Motika, Gerard M. Salem | 2020-03-10 |
| 10545190 | Circuit structures to resolve random testability | Raghu G. GopalaKrishnaSetty, Spencer K. Millican | 2020-01-28 |
| 10545188 | Functional diagnostics based on dynamic selection of alternate clocking | Franco Motika, Gerard M. Salem | 2020-01-28 |
| 10527674 | Circuit structures to resolve random testability | Raghu G. GopalaKrishnaSetty, Spencer K. Millican | 2020-01-07 |
| 10502782 | Synthesis for random testability using unreachable states in integrated circuits | Victor N. Kravets, Haoxing Ren, Spencer K. Millican | 2019-12-10 |
| 10386912 | Operating pulsed latches on a variable power supply | Steven M. Douskey, Raghu G. GopalaKrishnaSetty, Hari Krishnan Rajeev, James D. Warnock | 2019-08-20 |
| 10379159 | Minimization of over-masking in an on product multiple input signature register (OPMISR) | Steven M. Douskey, Michael J. Hamilton, Amanda R. Kaufer, Matthew B. Schallhorn | 2019-08-13 |
| 10371747 | Physically aware scan diagnostic logic and power saving circuit insertion | William V. Huott, Ankit N. Kagliwal, Robert C. Redburn | 2019-08-06 |
| 10371750 | Minimization of over-masking in an on product multiple input signature register (OPMISR) | Steven M. Douskey, Matthew B. Schallhorn | 2019-08-06 |
| 10371749 | Removal of over-masking in an on product multiple input signature register (OPMISR) test | Steven M. Douskey, Amanda R. Kaufer, Michael J. Hamilton, Matthew B. Schallhorn | 2019-08-06 |
| 10345380 | Implementing over-masking removal in an on product multiple input signature register (OPMISR) test due to common channel mask scan registers (CMSR) loading | Steven M. Douskey, Matthew B. Schallhorn, Amanda R. Kaufer, Michael J. Hamilton | 2019-07-09 |