Issued Patents All Time
Showing 1–25 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11017137 | Efficient projection based adjustment evaluation in static timing analysis of integrated circuits | Chaitanya Ravindra Peddawad, Jeffrey G. Hemmett, Jason D. Morsey, Steven E. Washburn, Peter C. Elmendorf +1 more | 2021-05-25 |
| 10970447 | Leverage cycle stealing within optimization flows | Nathaniel D. Hieter, Alexander J. Suess | 2021-04-06 |
| 10929567 | Parallel access to running electronic design automation (EDA) application | Douglas Keller, Debjit Sinha, Richard W. Taggart, Natesan Venkateswaran | 2021-02-23 |
| 10902167 | Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuits | Chaitanya Ravindra Peddawad, Alexander J. Suess, Hemlata Gupta, Gregory M. Schaeffer | 2021-01-26 |
| 10891412 | Offline analysis of hierarchical electronic design automation derived data | SheshaShayee K. Raghunathan, Thomas S. Guzowski, Nathan C. Buck, Jack DiLullo, Debra Dean | 2021-01-12 |
| 10747925 | Variable accuracy incremental timing analysis | Jeffrey G. Hemmett, Natesan Venkateswaran, Debjit Sinha, Eric A. Foreman, Chaitanya Ravindra Peddawad | 2020-08-18 |
| 10606970 | Selection of corners and/or margins using statistical static timing analysis of an integrated circuit | Eric A. Foreman, Jeffrey G. Hemmett, Gregory M. Schaeffer, Stephen G. Shuma, Alexander J. Suess +3 more | 2020-03-31 |
| 10552562 | Leverage cycle stealing within optimization flows | Nathaniel D. Hieter, Alexander J. Suess | 2020-02-04 |
| 10540465 | Leverage cycle stealing within optimization flows | Nathaniel D. Hieter, Alexander J. Suess | 2020-01-21 |
| 10387682 | Parallel access to running electronic design automation (EDA) application | Douglas Keller, Debjit Sinha, Richard W. Taggart, Natesan Venkateswaran | 2019-08-20 |
| 10380289 | Multi-sided variations for creating integrated circuits | Robert J. Allen, Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Gregory M. Schaeffer +4 more | 2019-08-13 |
| 10380286 | Multi-sided variations for creating integrated circuits | Robert J. Allen, Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Gregory M. Schaeffer +4 more | 2019-08-13 |
| 10372851 | Independently projecting a canonical clock | Nathan C. Buck, Sean Michael Carey, Peter C. Elmendorf, Eric A. Foreman, Jeffrey G. Hemmett +3 more | 2019-08-06 |
| 10354046 | Programmable clock division methodology with in-context frequency checking | Naiju K. Abdul, Jennifer E. Basile, Hemlata Gupta, Jeremy J. Leitzen, Stephen G. Shuma +3 more | 2019-07-16 |
| 10346569 | Multi-sided variations for creating integrated circuits | Robert J. Allen, Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Gregory M. Schaeffer +4 more | 2019-07-09 |
| 10325059 | Incremental common path pessimism analysis | Tsung-Wei Huang, Vasant Rao, Debjit Sinha, Natesan Venkateswaran | 2019-06-18 |
| 10318683 | Clock domain-independent abstracts | Naiju K. Abdul, Adil Bhanji, Jack DiLullo, Jeremy J. Leitzen, Manish Verma | 2019-06-11 |
| 10289776 | Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit | Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Gregory M. Schaeffer, Stephen G. Shuma +3 more | 2019-05-14 |
| 10216875 | Leverage cycle stealing within optimization flows | Nathaniel D. Hieter, Alexander J. Suess | 2019-02-26 |
| 10169526 | Incremental parasitic extraction for coupled timing and power optimization | Tsz-Mei Ko, Ravichander Ledalla, Alice H. Lee, Adam P. Matheny, Jose L. Neves +1 more | 2019-01-01 |
| 10169503 | Callback based constraint processing for clock domain independence | Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Alex Rubin, Manish Verma | 2019-01-01 |
| 10031985 | Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit | Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Gregory M. Schaeffer, Stephen G. Shuma +3 more | 2018-07-24 |
| 10013516 | Selection of corners and/or margins using statistical static timing analysis of an integrated circuit | Eric A. Foreman, Jeffrey G. Hemmett, Gregory M. Schaeffer, Stephen G. Shuma, Alexander J. Suess +3 more | 2018-07-03 |
| 9985843 | Efficient parallel processing of a network with conflict constraints between nodes | Hemlata Gupta, David J. Hathaway, Ronald D. Rose | 2018-05-29 |
| 9977850 | Callback based constraint processing for clock domain independence | Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Alex Rubin, Manish Verma | 2018-05-22 |