Issued Patents All Time
Showing 25 most recent of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411996 | Hardware-based implementation of secure hash algorithms | Manoj Kumar, Silvia M. Mueller, Debapriya Chatterjee, Niels Fricke, Maarten J. Boersma +1 more | 2025-09-09 |
| 12164921 | Comparing hash values computed at function entry and exit for increased security | Jose E. Moreira, Arnold Flores, Debapriya Chatterjee | 2024-12-10 |
| 12008150 | Encrypted data processing design including cleartext register files | Jessica Hui-Chun Tseng, Jose E. Moreira, Pratap C. Pattnaik, Manoj Kumar, Gianfranco Bilardi | 2024-06-11 |
| 11907361 | System and method for supporting secure objects using a memory access control monitor | Richard H. Boivie, Kenneth A. Goldman, William E. Hall, Guerney D. H. Hunt, Bhushan P. Jain +5 more | 2024-02-20 |
| 11900116 | Loosely-coupled slice target file data | Dung Q. Nguyen, Brian W. Thompto, Jose E. Moreira, Jessica Hui-Chun Tseng, Pratap C. Pattnaik +1 more | 2024-02-13 |
| 11868275 | Encrypted data processing design including local buffers | Manoj Kumar, Gianfranco Bilardi, Jose E. Moreira, Pratap C. Pattnaik, Jessica Hui-Chun Tseng | 2024-01-09 |
| 11836493 | Memory access operations for large graph analytics | Manoj Kumar, Gianfranco Bilardi, Jose E. Moreira, Pratap C. Pattnaik, Jessica Hui-Chun Tseng | 2023-12-05 |
| 11663009 | Supporting large-word operations in a reduced instruction set computer (“RISC”) processor | Sandhya Koteshwara, Manoj Kumar, Jose E. Moreira, Pratap C. Pattnaik | 2023-05-30 |
| 11294685 | Instruction fusion using dependence analysis | Jessica Hui-Chun Tseng, Manoj Kumar, Jose E. Moreira, Pratap C. Pattnaik | 2022-04-05 |
| 11163528 | Reformatting matrices to improve computing efficiency | Manoj Kumar, Pratap C. Pattnaik, Jessica Hui-Chun Tseng, Jose E. Moreira | 2021-11-02 |
| 10956361 | Processor core design optimized for machine learning applications | Manoj Kumar, Pratap C. Pattnaik, Jessica Hui-Chun Tseng, Jose E. Moreira | 2021-03-23 |
| 10956167 | Mechanism for instruction fusion using tags | Jessica Hui-Chun Tseng, Manoj Kumar, Jose E. Moreira, Pratap C. Pattnaik | 2021-03-23 |
| 10936320 | Efficient performance of inner loops on a multi-lane processor | Manoj Kumar, Jose E. Moreira, Pratap C. Pattnaik, Jessica Hui-Chun Tseng | 2021-03-02 |
| 10628579 | System and method for supporting secure objects using a memory access control monitor | Richard H. Boivie, Kenneth A. Goldman, William E. Hall, Guerney Douglass Holloway Hunt, Bhushan P. Jain +5 more | 2020-04-21 |
| 9928158 | Redundant transactions for detection of timing sensitive errors | Harold W. Cain, III, David M. Daly, Michael C. Huang, Jose E. Moreira, Mauricio J. Serrano | 2018-03-27 |
| 9778967 | Sophisticated run-time system for graph processing | William P. Horn, Joefon Jann, Manoj Kumar, Jose E. Moreira, Pratap C. Pattnaik +3 more | 2017-10-03 |
| 9772890 | Sophisticated run-time system for graph processing | William P. Horn, Joefon Jann, Manoj Kumar, Jose E. Moreira, Pratap C. Pattnaik +3 more | 2017-09-26 |
| 9696927 | Memory transaction having implicit ordering effects | Harold W. Cain, III, Maged M. Michael, Pratap C. Pattnaik, Derek E. Williams | 2017-07-04 |
| 9696928 | Memory transaction having implicit ordering effects | Harold W. Cain, III, Maged M. Michael, Pratap C. Pattnaik, Derek E. Williams | 2017-07-04 |
| 9619356 | Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processor | Harold W. Cain, III, David M. Daly, Michael C. Huang, Jose E. Moreira, Mauricio J. Serrano | 2017-04-11 |
| 9459979 | Detection of hardware errors using redundant transactions for system test | Harold W. Cain, III, David M. Daly, Michael C. Huang, Jose E. Moreira, Mauricio J. Serrano | 2016-10-04 |
| 9400700 | Optimized system for analytics (graphs and sparse matrices) operations | William P. Horn, Joefon Jann, Manoj Kumar, Jose E. Moreira, Pratap C. Pattnaik +3 more | 2016-07-26 |
| 9304863 | Transactions for checkpointing and reverse execution | Harold W. Cain, III, David M. Daly, Jose E. Moreira, Mauricio J. Serrano | 2016-04-05 |
| 9304835 | Optimized system for analytics (graphs and sparse matrices) operations | William P. Horn, Joefon Jann, Manoj Kumar, Jose E. Moreira, Pratap C. Pattnaik +3 more | 2016-04-05 |
| 9251014 | Redundant transactions for detection of timing sensitive errors | Harold W. Cain, III, David M. Daly, Michael C. Huang, Jose E. Moreira, Mauricio J. Serrano | 2016-02-02 |