Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11664068 | Single ended current mode sense amplifier with feedback inverter | Rajiv V. Joshi, Sudipto Chakraborty, Alexander Fritsch | 2023-05-30 |
| 11527283 | Single ended bitline current sense amplifiers | Sudipto Chakraborty, Rajiv V. Joshi, Alexander Fritsch | 2022-12-13 |
| 10579773 | Layouting of interconnect lines in integrated circuits | Joachim Keinert, Jens Noack, Monika Strohmer | 2020-03-03 |
| 10417377 | Layouting of interconnect lines in integrated circuits | Joachim Keinert, Jens Noack, Monika Strohmer | 2019-09-17 |
| 10013521 | Layouting of interconnect lines in integrated circuits | Joachim Keinert, Jens Noack, Monika Strohmer | 2018-07-03 |
| 9922154 | Enabling an incremental sign-off process using design data | Hans-Werner Anderson, Joachim Keinert, Jens Noack | 2018-03-20 |
| 9837143 | NAND-based write driver for SRAM | Hans-Werner Anderson, Thomas Kalla, Jens Noack | 2017-12-05 |
| 9761304 | Write-bitline control in multicore SRAM arrays | Joachim Keinert, Jens Noack, Monika Strohmer | 2017-09-12 |
| 8560983 | Incorporating synthesized netlists as subcomponents in a hierarchical custom design | Uwe Brandt, Thomas Makowski, Christoph Wandel | 2013-10-15 |
| 8332453 | Shifter with all-one and all-zero detection using a portion of partially shifted vector and shift amount in parallel to generated shifted result | Maarten J. Boersma, Silvia M. Mueller, Jochen Preiss | 2012-12-11 |
| 8286115 | Fast routing of custom macros | Maarten J. Boersma, Wilhelm Haller, Armin Windschiegl | 2012-10-09 |
| 7913132 | System and method for scanning sequential logic elements | Tobias Gemmeke, Dieter Wendel, Jens Leenstra | 2011-03-22 |
| 7873687 | Method for calculating a result of a division with a floating point unit with fused multiply-add | Guenter Gerwig | 2011-01-18 |
| 6292819 | Binary and decimal adder unit | Wolfgang Friedrich Bultmann, Wilhelm Haller, Alexander Wörner | 2001-09-18 |
| 5944772 | Combined adder and logic unit | Juergen Haas, Wilhelm Haller, Ulrich Krauch, Thomas Ludwig | 1999-08-31 |
| 5928319 | Combined binary/decimal adder unit | Wilhelm Haller, Ulrich Krauch, Thomas Ludwig | 1999-07-27 |