Issued Patents All Time
Showing 25 most recent of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9035399 | Structure for facilitating the simultaneous silicidation of a polysilicon gate and source/drain of a semiconductor device | Shaofeng Yu, Steven A. Vitale, Joe G. Tran | 2015-05-19 |
| 8574980 | Method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device | Shaofeng Yu, Steven A. Vitale, Craig Huffman | 2013-11-05 |
| 8372703 | Gate dielectric first replacement gate processes and integrated circuits therefrom | Brian K. Kirkpatrick, Shaofeng Yu | 2013-02-12 |
| 8273645 | Method to attain low defectivity fully silicided gates | Mark Visokay, Richard L. Guldi, Yaw S. Obeng | 2012-09-25 |
| 7960280 | Process method to fully salicide (FUSI) both N-poly and P-poly on a CMOS flow | Frank Scott Johnson | 2011-06-14 |
| 7943456 | Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom | Shaofeng Yu, Brian K. Kirkpatrick | 2011-05-17 |
| 7910422 | Reducing gate CD bias in CMOS processing | Jinhan Choi, Frank Scott Johnson | 2011-03-22 |
| 7892906 | Method for forming CMOS transistors having FUSI gate electrodes and targeted work functions | Frank Scott Johnson | 2011-02-22 |
| 7838356 | Gate dielectric first replacement gate processes and integrated circuits therefrom | Brian K. Kirkpatrick, Shaofeng Yu | 2010-11-23 |
| 7763540 | Method of forming a silicided gate utilizing a CMP stack | Frank Scott Johnson | 2010-07-27 |
| 7727842 | Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device | Shaofeng Yu, Steven A. Vitale, Joe G. Tran | 2010-06-01 |
| 7670952 | Method of manufacturing metal silicide contacts | Yaw S. Obeng, Juanita DeLoach | 2010-03-02 |
| 7601575 | Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance | Haowen Bu, Shashank S. Ekbote, Rajesh Khamankar, Shaoping Tang | 2009-10-13 |
| 7585738 | Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device | Shaofeng Yu, Jiong-Ping Lu | 2009-09-08 |
| 7504339 | Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits | Zhihao Chen, Brian K. Kirkpatrick, Jeff White, Edmund G. Russell, Jon Holt +1 more | 2009-03-17 |
| 7448395 | Process method to facilitate silicidation | Jiong-Ping Lu, Lindsey Hall, Vivian Liu, Clint Montgomery, Scott Francis Johnson | 2008-11-11 |
| 7396716 | Method to obtain fully silicided poly gate | Shaofeng Yu, Joe G. Tran | 2008-07-08 |
| 7244642 | Method to obtain fully silicided gate electrodes | Steven A. Vitale, Hyesook Hong | 2007-07-17 |
| 7112497 | Multi-layer reducible sidewall process | Vivian Liu, Amitava Chatterjee | 2006-09-26 |
| 7078347 | Method for forming MOS transistors with improved sidewall structures | Scott Francis Johnson, Reji Koshy | 2006-07-18 |
| 7045410 | Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI) | Amitava Chatterjee | 2006-05-16 |
| 6930007 | Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance | Haowen Bu, Shashank S. Ekbote, Rajesh Khamankar, Shaoping Tang | 2005-08-16 |
| 6930018 | Shallow trench isolation structure and method | Zhihao Chen, Shashank S. Ekbote, Brian Trentman | 2005-08-16 |
| 6917093 | Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits | Zhihao Chen, Brian K. Kirkpatrick, Jeff White, Edmund G. Russell, Jon Holt +1 more | 2005-07-12 |
| 6905943 | Forming a trench to define one or more isolation regions in a semiconductor structure | Juanita DeLoach, Brian Trentman, Troy A. Yocum | 2005-06-14 |