Issued Patents All Time
Showing 1–25 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9684629 | Efficient calibration of a low power parallel data communications channel | Timothy O. Dickson, Daniel M. Dreps, Douglas J. Joseph | 2017-06-20 |
| 9558139 | System interconnect dynamic scaling handshake using spare bit-lane | Daniel M. Dreps, Anand Haridass, Prasanna Jayaraman | 2017-01-31 |
| 9552319 | System interconnect dynamic scaling handshake using spare bit-lane | Daniel M. Dreps, Anand Haridass, Prasanna Jayaraman | 2017-01-24 |
| 9529406 | System interconnect dynamic scaling by lane width and operating frequency balancing | Daniel M. Dreps, Anand Haridass, Prasanna Jayaraman | 2016-12-27 |
| 9524013 | System interconnect dynamic scaling by lane width and operating frequency balancing | Daniel M. Dreps, Anand Haridass, Prasanna Jayaraman | 2016-12-20 |
| 9459982 | Bus interface optimization by selecting bit-lanes having best performance margins | Daniel M. Dreps, Anand Haridass, Prasanna Jayaraman | 2016-10-04 |
| 9411750 | Efficient calibration of a low power parallel data communications channel | Timothy O. Dickson, Daniel M. Dreps, Douglas J. Joseph | 2016-08-09 |
| 9325534 | Configurable differential to single ended IO | Kevin C. Gower, Robert B. Tremaine, Kenneth L. Wright | 2016-04-26 |
| 9324031 | System interconnect dynamic scaling by predicting I/O requirements | Daniel M. Dreps, Anand Haridass, Prasanna Jayaraman, David J. Krolak | 2016-04-26 |
| 9324030 | System interconnect dynamic scaling by predicting I/O requirements | Daniel M. Dreps, Anand Haridass, Prasanna Jayaraman, David J. Krolak | 2016-04-26 |
| 9244799 | Bus interface optimization by selecting bit-lanes having best performance margins | Daniel M. Dreps, Anand Haridass, Prasanna Jayaraman | 2016-01-26 |
| 9001842 | Parallel receiver interface with receiver redundancy | Timothy O. Dickson, Douglas J. Joseph | 2015-04-07 |
| 8898503 | Low latency data transfer between clock domains operated in various synchronization modes | Daniel M. Dreps, Hubert Harrer, Pak-kin Mak, Ching-Lung Tong, Tobias Webel +1 more | 2014-11-25 |
| 8898504 | Parallel data communications mechanism having reduced power continuously calibrated lines | Steven J. Baumgartner, Susan M. Eickhoff, Michael B. Spear | 2014-11-25 |
| 8861513 | Fault tolerant parallel receiver interface with receiver redundancy | Timothy O. Dickson, Daniel M. Dreps | 2014-10-14 |
| 8862944 | Isolation of faulty links in a transmission medium | John Steven Dodson, Michele M. Franceschini, Kevin C. Gower, Ashish Jagmohan, Luis A. Lastras-Montano +1 more | 2014-10-14 |
| 8767531 | Dynamic fault detection and repair in a data communications mechanism | William R. Kelly, Robert J. Reese, Susan M. Rubow, Michael B. Spear | 2014-07-01 |
| 8681839 | Calibration of multiple parallel data communications lines for high skew conditions | John F. Bulzacchelli, Timothy O. Dickson, Robert J. Reese, Michael B. Spear | 2014-03-25 |
| 8139430 | Power-on initialization and test for a cascade interconnect memory system | Peter Buchmann, Kevin C. Gower, Robert J. Reese, Eric E. Retter, Martin Schmatz +3 more | 2012-03-20 |
| 8082474 | Bit shadowing in a memory system | Daniel M. Dreps, Kevin C. Gower, Robert J. Reese | 2011-12-20 |
| 8082475 | Enhanced microprocessor interconnect with bit shadowing | Daniel M. Dreps, Kevin C. Gower, Robert J. Reese | 2011-12-20 |
| 8050174 | Self-healing chip-to-chip interface | Wiren D. Becker, Daniel M. Dreps, Anand Haridass, Robert J. Reese | 2011-11-01 |
| 8018837 | Self-healing chip-to-chip interface | Wiren D. Becker, Daniel M. Dreps, Anand Haridass, Robert J. Reese | 2011-09-13 |
| 8004335 | Phase interpolator system and associated methods | Kyu-hyoun Kim, Paul W. Coteus, Daniel M. Dreps | 2011-08-23 |
| 8001412 | Combined alignment scrambler function for elastic interface | Robert J. Reese, Michael B. Spear | 2011-08-16 |