Issued Patents All Time
Showing 25 most recent of 213 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426307 | Dual metal gate structures on nanoribbon semiconductor devices | Yang-Chun Cheng, Dax M. Crum | 2025-09-23 |
| 12376353 | Source/drain regions in integrated circuit structures | Sean T. Ma, Guillaume Bouche | 2025-07-29 |
| 12328936 | Gate spacing in integrated circuit structures | Guillaume Bouche, Sean T. Ma | 2025-06-10 |
| 12327791 | Integrated circuit structures with gate cuts above buried power rails | — | 2025-06-10 |
| 12315805 | Self-aligned lateral contacts | Yang-Chun Cheng, Shaestagir Chowdhury, Guillaume Bouche | 2025-05-27 |
| 12237388 | Transistor arrangements with stacked trench contacts and gate straps | Changyok Park, Guillaume Bouche, Hyuk-Ju Ryu, Charles H. Wallace, Mohit K. HARAN | 2025-02-25 |
| 12211786 | Stacked vias with bottom portions formed using selective growth | Guillaume Bouche | 2025-01-28 |
| 12211898 | Device contact sizing in integrated circuit structures | Guillaume Bouche, Sean T. Ma | 2025-01-28 |
| 12199161 | Contact over active gate structures with tapered gate or trench contact for advanced integrated circuit structure fabrication | Charles H. Wallace, Mohit K. HARAN | 2025-01-14 |
| 12148751 | Use of a placeholder for backside contact formation for transistor arrangements | Anand S. Murthy, Mauro J. Kobrinsky, Guillaume Bouche | 2024-11-19 |
| 12094822 | Buried power rails with self-aligned vias to trench contacts | Guillaume Bouche, Changyok Park | 2024-09-17 |
| 11973121 | Device contacts in integrated circuit structures | Guillaume Bouche, Mwilwa Tambwe, Sean T. Ma, Piyush Mohan Sinha | 2024-04-30 |
| 11916106 | Source/drain regions in integrated circuit structures | Sean T. Ma, Guillaume Bouche | 2024-02-27 |
| 11916010 | Back end of line integration for self-aligned vias | Guillaume Bouche | 2024-02-27 |
| 11749715 | Isolation regions in integrated circuit structures | Guillaume Bouche, Sean T. Ma | 2023-09-05 |
| 11508847 | Transistor arrangements with metal gate cuts and recessed power rails | Sean T. Ma, Piyush Mohan Sinha | 2022-11-22 |
| 11482524 | Gate spacing in integrated circuit structures | Guillaume Bouche, Sean T. Ma | 2022-10-25 |
| 11450736 | Source/drain regions in integrated circuit structures | Sean T. Ma, Guillaume Bouche | 2022-09-20 |
| 11430866 | Device contact sizing in integrated circuit structures | Guillaume Bouche, Sean T. Ma | 2022-08-30 |
| 11342409 | Isolation regions in integrated circuit structures | Guillaume Bouche, Sean T. Ma | 2022-05-24 |
| 11264463 | Multiple fin finFET with low-resistance gate structure | Guillaume Bouche | 2022-03-01 |
| 10700170 | Multiple fin finFET with low-resistance gate structure | Guillaume Bouche | 2020-06-30 |
| 10644136 | Merged gate and source/drain contacts in a semiconductor device | Guillaume Bouche | 2020-05-05 |
| 10396026 | Precut metal lines | Guillaume Bouche, Mark A. Zaleski | 2019-08-27 |
| 10262941 | Devices and methods for forming cross coupled contacts | Guillaume Bouche, Jason E. Stephens, Tuhin Guha Neogi, Kai Sun, Deniz E. Civay +1 more | 2019-04-16 |