Issued Patents All Time
Showing 1–25 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11018084 | Managed integrated circuit power supply distribution | Jeffrey Douglas Brown, Kirk D. Peterson, John E. Sheets, II | 2021-05-25 |
| 10580730 | Managed integrated circuit power supply distribution | Jeffrey Douglas Brown, Kirk D. Peterson, John E. Sheets, II | 2020-03-03 |
| 10311966 | On-chip diagnostic circuitry monitoring multiple cycles of signal samples | Derick G. Behrends, Todd A. Christensen, Jeffrey M. Scherer | 2019-06-04 |
| 9715905 | Detecting maximum voltage between multiple power supplies for memory testing | Derick G. Behrends, Todd A. Christensen, Jeffrey M. Scherer | 2017-07-25 |
| 9712170 | Level-shifting latch | Steven J. Baumgartner, Charles P. Geer, David P. Paulsen, David W. Siljenberg, Alan P. Wagstaff | 2017-07-18 |
| 9583938 | Electrostatic discharge protection device with power management | Derick G. Behrends, Todd A. Christensen, David W. Siljenberg | 2017-02-28 |
| 9553584 | Level-shifting latch | Steven J. Baumgartner, Charles P. Geer, David P. Paulsen, David W. Siljenberg, Alan P. Wagstaff | 2017-01-24 |
| 9496712 | Electrostatic discharge protection device with power management | Derick G. Behrends, Todd A. Christensen, David W. Siljenberg | 2016-11-15 |
| 9424389 | Implementing enhanced performance dynamic evaluation circuit by combining precharge and delayed keeper | Derick G. Behrends, Todd A. Christensen, Jesse D. Smith | 2016-08-23 |
| 9396303 | Implementing enhanced performance dynamic evaluation circuit by combining precharge and delayed keeper | Derick G. Behrends, Todd A. Christensen, Jesse D. Smith | 2016-07-19 |
| 8643421 | Implementing low power, single master-slave elastic buffer | Morgan D. Davis, Matthew R. Ellavsky, Kent Harold Haselhorst, Kerry Christopher Imming, Mark G. Veldhuizen | 2014-02-04 |
| 8513815 | Implementing integrated circuit mixed double density and high performance wire structure | Todd A. Christensen, John E. Sheets, II | 2013-08-20 |
| 7764531 | Implementing precise resistance measurement for 2D array efuse bit cell using differential sense amplifier, balanced bitlines, and programmable reference resistor | Toshiaki Kirihata, Phil C. Paone, Brian Joy Reed, John M. Safran, David Edward Schmitt +1 more | 2010-07-27 |
| 7733722 | Apparatus for implementing eFuse sense amplifier testing without blowing the eFuse | David H. Allen, Louis Bernard Bushard, Phil C. Paone, Gregory J. Uhlmann | 2010-06-08 |
| 7729188 | Method and circuit for implementing enhanced eFuse sense circuit | Phil C. Paone, Brian Joy Reed, David Edward Schmitt, Gregory J. Uhlmann | 2010-06-01 |
| 7725844 | Method and circuit for implementing eFuse sense amplifier verification | Phil C. Paone, Brian Joy Reed, David Edward Schmitt, Gregory J. Uhlmann | 2010-05-25 |
| 7689950 | Implementing Efuse sense amplifier testing without blowing the Efuse | David H. Allen, Louis Bernard Bushard, Phil C. Paone, Gregory J. Uhlmann | 2010-03-30 |
| 7562267 | Methods and apparatus for testing a memory | Louis Bernard Bushard, Akihiko Fukui, Garrett Stephen Koch | 2009-07-14 |
| 7535750 | Asymmetrical random access memory cell, and a memory comprising asymmetrical memory cells | Otto Wagner, Sebastian Ehrenreich, Torsten Mahnke | 2009-05-19 |
| 7532057 | Electrically programmable fuse sense circuit | David H. Allen, Phil C. Paone, David Edward Schmitt, Gregory J. Uhlmann | 2009-05-12 |
| 7528646 | Electrically programmable fuse sense circuit | David H. Allen, Phil C. Paone, David Edward Schmitt, Gregory J. Uhlmann | 2009-05-05 |
| 7506282 | Apparatus and methods for predicting and/or calibrating memory yields | Chad A. Adams, George Paulik | 2009-03-17 |
| 7489572 | Method for implementing eFuse sense amplifier testing without blowing the eFuse | David H. Allen, Louis Bernard Bushard, Phil C. Paone, Gregory J. Uhlmann | 2009-02-10 |
| 7400550 | Delay mechanism for unbalanced read/write paths in domino SRAM arrays | Chad A. Adams, Derick G. Behrends, George Paulik | 2008-07-15 |
| 7318209 | Pulse-width limited chip clock design | David William Boerstler, Dieter Wendel | 2008-01-08 |