Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10256248 | Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof | Zhenyu Lu, Jixin Yu, Johann Alsmeier, Fumiaki Toyama, Yuki Mizutani +5 more | 2019-04-09 |
| 10249640 | Within-array through-memory-level via structures and method of making thereof | Jixin Yu, Zhenyu Lu, Kensuke Yamaguchi, Hiroyuki Ogawa, Daxin Mao +2 more | 2019-04-02 |
| 10115440 | Word line contact regions for three-dimensional non-volatile memory | Qui Vi Nguyen, Kenneth Louie, Anirudh Amarnath, Jixin Yu, Yen-Lung Li +2 more | 2018-10-30 |
| 9947682 | Three dimensional non-volatile memory with separate source lines | Nima Mokhlesi | 2018-04-17 |
| 9922716 | Architecture for CMOS under array | Chia-Lin Hsiung, Yanbin An, Fumiaki Toyama | 2018-03-20 |
| 9875156 | Data storage device with a memory die that includes an interleaver | Eran Sharon, Ariel Navon, Wanfang Tsai, Idan Alrod | 2018-01-23 |
| 9721671 | Memory device which performs verify operations using different sense node pre-charge voltages and a common discharge period | Jong Hak Yuh, Kwang Ho Kim, YenLung Li, Farookh Moogat | 2017-08-01 |
| 9293195 | Compact high speed sense amplifier for non-volatile memory | Man Lung Mui, Jongmin Park, Hao Thai Nguyen, Juan Lee, Seungpil Lee | 2016-03-22 |
| 7974134 | Voltage generator to compensate sense amplifier trip point over temperature in non-volatile memory | Fanglin Zhang, Jong Park, Man Lung Mui, Seungpil Lee | 2011-07-05 |