Issued Patents All Time
Showing 176–200 of 404 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9769923 | Interposers | Bong-Sub Lee, Charles G. Woychik, Liang Wang, Laura Wills Mirkarimi, Arkalgud R. Sitaram | 2017-09-19 |
| 9761517 | Porous alumina templates for electronic packages | Rajesh Katkar, Belgacem Haba, Ilyas Mohammed | 2017-09-12 |
| 9754866 | Reversed build-up substrate for 2.5D | Liang Wang, Rajesh Katkar, Hong Shen, Belgacem Haba | 2017-09-05 |
| 9741696 | Thermal vias disposed in a substrate proximate to a well thereof | Rajesh Katkar, Arkalgud R. Sitaram | 2017-08-22 |
| 9741620 | Structures and methods for reliable packages | Guilian Gao, Liang Wang, Hong Shen, Arkalgud R. Sitaram | 2017-08-22 |
| 9728527 | Multiple bond via arrays of different wire heights on a same substrate | Rajesh Katkar | 2017-08-08 |
| 9711401 | Reliable packaging and interconnect structures | Belgacem Haba, Craig Mitchell | 2017-07-18 |
| 9691702 | Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates | Charles G. Woychik, Arkalgud R. Sitaram, Hong Shen, Zhuowen Sun, Liang Wang +1 more | 2017-06-27 |
| 9685420 | Localized sealing of interconnect structures in small gaps | Rajesh Katkar, Arkalgud R. Sitaram | 2017-06-20 |
| 9685401 | Structures for heat dissipating interposers | Pezhman Monadgemi, Terrence Caskey, Fatima Lina Ayatollahi, Belgacem Haba, Charles G. Woychik +1 more | 2017-06-20 |
| 9673124 | Device and method for localized underfill | Liang Wang, Rajesh Katkar, Charles G. Woychik | 2017-06-06 |
| 9666521 | Ultra high performance interposer | Zhuowen Sun | 2017-05-30 |
| 9666514 | High performance compliant substrate | Rajesh Katkar | 2017-05-30 |
| 9659858 | Low-stress vias | Ilyas Mohammed, Belgacem Haba | 2017-05-23 |
| 9646917 | Low CTE component with wire bond interconnects | Rajesh Katkar | 2017-05-09 |
| 9634412 | Connector structures and methods | Craig Mitchell | 2017-04-25 |
| 9633971 | Structures and methods for low temperature bonding using nanoparticles | — | 2017-04-25 |
| 9615451 | Porous alumina templates for electronic packages | Rajesh Katkar, Belgacem Haba, Ilyas Mohammed | 2017-04-04 |
| 9607928 | Method and structures for via substrate repair and assembly | — | 2017-03-28 |
| 9601467 | Microelectronic package with horizontal and vertical interconnections | Rajesh Katkar | 2017-03-21 |
| 9601398 | Thin wafer handling and known good die test method | Charles G. Woychik, Se Young Yang, Pezhman Monadgemi, Terrence Caskey | 2017-03-21 |
| 9583456 | Multiple bond via arrays of different wire heights on a same substrate | Rajesh Katkar | 2017-02-28 |
| 9583426 | Multi-layer substrates suitable for interconnection between circuit modules | Hong Shen, Liang Wang, Gabriel Z. Guevara, Rajesh Katkar, Laura Wills Mirkarimi | 2017-02-28 |
| 9583417 | Via structure for signal equalization | Zhuowen Sun, Yong-Syuan Chen | 2017-02-28 |
| 9570385 | Method for fabrication of interconnection circuitry with electrically conductive features passing through a support and comprising core portions formed using nanoparticle-containing inks | Bong-Sub Lee, Charles G. Woychik, Liang Wang, Laura Wills Mirkarimi, Arkalgud R. Sitaram | 2017-02-14 |