Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11183594 | Dual gate control for trench shaped thin film transistors | Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Shriram Shivaraman +2 more | 2021-11-23 |
| 11171240 | Recessed thin-channel thin-film transistor | Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Tahir Ghani | 2021-11-09 |
| 11121073 | Through plate interconnect for a vertical MIM capacitor | Travis W. Lajoie, Abhishek A. Sharma, Juan G. Alzate-Vinasco, Chieh-Jen Ku, Shem Ogadhoh +6 more | 2021-09-14 |
| 11114446 | SRAM with hierarchical bit lines in monolithic 3D integrated chips | — | 2021-09-07 |
| 11094358 | Semiconductor chip manufacturing process for integrating logic circuitry, embedded DRAM and embedded non-volatile ferroelectric random access memory (FERAM) on a same semiconductor die | Ilya V. Karpov, Fatih Hamzaoglu, James S. Clarke | 2021-08-17 |
| 11088146 | Thin-film transistor embedded dynamic random-access memory | — | 2021-08-10 |
| 11031503 | Non-planar gate thin film transistor | Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Rafael Rios, Jack T. Kavalieros +1 more | 2021-06-08 |
| 11024356 | Apparatus for low power write and read operations for resistive memory | Liqiong Wei, Fatih Hamzaoglu, Nathaniel J. August, Blake C. Lin, Cyrille Dray | 2021-06-01 |
| 10964701 | Vertical shared gate thin-film transistor-based charge storage memory | Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Rafael Rios, Jack T. Kavalieros +1 more | 2021-03-30 |
| 10916583 | Monolithic integrated circuits with multiple types of embedded non-volatile memory devices | — | 2021-02-09 |
| 10811595 | Techniques for forming logic including integrated spin-transfer torque magnetoresistive random-access memory | Kevin J. Lee, Oleg Golonzka, Tahir Ghani, Ruth A. Brain | 2020-10-20 |
| 10672831 | High density memory architecture using back side metal layers | Patrick Morrow | 2020-06-02 |
| 10644064 | Logic chip including embedded magnetic tunnel junctions | Kevin J. Lee, Tahir Ghani, Joseph M. Steigerwald, John H. Epple | 2020-05-05 |
| 10541014 | Memory cells with enhanced tunneling magnetoresistance ratio, memory devices and systems including the same | Brian S. Doyle, Elijah V. Karpov, Kaan Oguz, Kevin P. O'Brien, Charles C. Kuo +2 more | 2020-01-21 |
| 10483321 | High density memory architecture using back side metal layers | Patrick Morrow | 2019-11-19 |
| 10438640 | Apparatus for low power write and read operations for resistive memory | Liqiong Wei, Fatih Hamzaoglu, Nathaniel J. August, Blake C. Lin, Cyrille Dray | 2019-10-08 |
| 10416217 | On-chip test circuit for magnetic random access memory (MRAM) | Sasikanth Manipatruni, Chia-Ching Lin, Ian A. Young | 2019-09-17 |
| 10068628 | Apparatus for low power write and read operations for resistive memory | Liqiong Wei, Fatih Hamzaoglu, Nathaniel J. August, Blake C. Lin, Cyrille Dray | 2018-09-04 |
| 9997563 | Logic chip including embedded magnetic tunnel junctions | Kevin J. Lee, Tahir Ghani, Joseph M. Steigerwald, John H. Epple | 2018-06-12 |
| 9978447 | Memory cell with improved write margin | Muhammad M. Khellah, Fatih Hamzaoglu | 2018-05-22 |
| 9953986 | Method and apparatus for improving read margin for an SRAM bit-cell | — | 2018-04-24 |
| 9865322 | Low resistance bitline and sourceline apparatus for improving read and write operations of a nonvolatile memory | Cyrille Dray, Blake C. Lin, Fatih Hamzaoglu, Liqiong Wei | 2018-01-09 |
| 9818933 | 6F2 non-volatile memory bitcell | — | 2017-11-14 |
| 9805790 | Memory cell with retention using resistive memory | Nathaniel J. August, Pulkit Jain, Stefan Rusu, Fatih Hamzaoglu, Rangharajan Venkatesan +4 more | 2017-10-31 |
| 9666268 | Apparatus for adjusting supply level to improve write margin of a memory cell | Muhammad M. Khellah, Fatih Hamzaoglu | 2017-05-30 |