Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7066657 | Optical subassembly | Douglas E. Crafts, Suresh Ramalingam, Brett M. Zaborsky, Siegfried Fleischer | 2006-06-27 |
| 7000434 | Method of creating an angled waveguide using lithographic techniques | — | 2006-02-21 |
| 6963684 | Multi-band arrayed waveguide grating with improved insertion loss and wavelength accuracy | Jyoti Kiron Bhardwaj, David J. Dougherty, Hiroaki Yamada | 2005-11-08 |
| 6928216 | Markings for aligning fiber optic bundle | Rama Shukla | 2005-08-09 |
| 6869882 | Method of creating a photonic via using deposition | — | 2005-03-22 |
| 6819836 | Photonic and electronic components on a shared substrate with through substrate communication | — | 2004-11-16 |
| 6788836 | Multi-level waveguide | — | 2004-09-07 |
| 6778727 | Optic switch | Suresh Ramalingam | 2004-08-17 |
| 6731843 | Multi-level waveguide | — | 2004-05-04 |
| 6687427 | Optic switch | Suresh Ramalingam | 2004-02-03 |
| 6650817 | Multi-level waveguide | — | 2003-11-18 |
| 6650823 | Method of creating a photonic via using fiber optic | — | 2003-11-18 |
| 6636671 | Markings for aligning fiber optic bundle | Rama Shukla | 2003-10-21 |
| 6633707 | Lithographically defined optic array | — | 2003-10-14 |
| 6450699 | Photonic and electronic components on a shared substrate | Rama Shukla | 2002-09-17 |
| 6331446 | Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state | Duane Cook, Suresh Ramalingam, Nagesh Vodrahalli | 2001-12-18 |
| 6278185 | Semi-additive process (SAP) architecture for organic leadless grid array packages | Kenzo Ishida, Brian Kaiser, Anant Vaidyanathan | 2001-08-21 |
| 6265300 | Wire bonding surface and bonding method | Ameet Bhansali, Gay M. Samuelson, Michael J. Gasparek, Shou H. Chen, Nicholas P. Mencinger +2 more | 2001-07-24 |
| 6248951 | Dielectric decal for a substrate of an integrated circuit package | Nagesh Vodrahalli, Brian Kaiser | 2001-06-19 |
| 6219910 | Method for cutting integrated circuit dies from a wafer which contains a plurality of solder bumps | — | 2001-04-24 |
| 5567981 | Bonding pad structure having an interposed rigid layer | Ameet Bhansali, Gay M. Samuelson, Michael J. Gasparek, Shou H. Chen, Nicholas P. Mencinger +2 more | 1996-10-22 |
| 5492235 | Process for single mask C4 solder bump fabrication | Douglas E. Crafts, Caroline Susan Lee | 1996-02-20 |
| 5047367 | Process for formation of a self aligned titanium nitride/cobalt silicide bilayer | Chin-Shih Wei, David B. Fraser | 1991-09-10 |
| 4966868 | Process for selective contact hole filling including a silicide plug | Chih-Shih Wei, David B. Fraser | 1990-10-30 |