KI

Kenzo Ishida

IN Intel: 8 patents #4,870 of 30,777Top 20%
JU Jds Uniphase: 4 patents #116 of 940Top 15%
AC Ai & Di Co.: 2 patents #2 of 6Top 35%
Overall (All Time): #354,552 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7724990 Fiber array unit with integrated optical power monitor 2010-05-25
7330620 Low loss funnel-type PLC optical splitter with input cladding mode absorption structure and/or output segmented taper structure Alan Tafapolsky, Takaharu Fujiyama 2008-02-12
7171743 Apparatus and method for warpage compensation of a display panel substrate assembly 2007-02-06
6798137 Apparatus and method for warpage compensation of a display panel substrate assembly 2004-09-28
6785148 Easy mount socket Shuji Inoue, Kinya Ichikawa, Kenji Takahashi 2004-08-31
6697553 Compact, low insertion loss, high yield arrayed waveguide grating Jyoti Kiron Bhardwaj, Robert J. Brainard, David J. Chapman, Douglas E. Crafts, Zi-Wen Dong +13 more 2004-02-24
6664511 Package for optical components Douglas E. Crafts, James F. Farrell, Mark Farrelly, Suresh Ramalingam 2003-12-16
6665475 Precision fiber optic alignment and attachment apparatus 2003-12-16
6606425 Transfer molded packages with embedded thermal insulation Douglas E. Crafts, David J. Chapman, Duane Cook, James F. Farrell, Suresh Ramalingam +1 more 2003-08-12
6422303 Silent heat exchanger and fan assembly Shinya Endo, Daryl J. Nelson 2002-07-23
6278185 Semi-additive process (SAP) architecture for organic leadless grid array packages Venkatesan Murali, Brian Kaiser, Anant Vaidyanathan 2001-08-21
6173576 Cooling unit for an integrated circuit package Shuji Inoue 2001-01-16
6020561 Printed circuit substrate with solder formed on pad-on-via and pad-off-via contacts thereof Yohko Mashimoto, Kinya Ichikawa 2000-02-01
5660321 Method for controlling solder bump height and volume for substrates containing both pad-on and pad-off via contacts Yohko Mashimoto, Kinya Ichikawa 1997-08-26