Issued Patents All Time
Showing 76–100 of 134 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8030197 | Recessed channel array transistor (RCAT) in replacement metal gate (RMG) logic flow | Brian S. Doyle, Gilbert Dewey, Ravi Pillarisetty, Nick Lindert, Dinesh Somasekhar | 2011-10-04 |
| 8030163 | Reducing external resistance of a multi-gate device using spacer processing techniques | Ravi Pillarisetty, Brian S. Doyle, Jack T. Kavalieros | 2011-10-04 |
| 7898041 | Block contact architectures for nanoscale channel transistors | Marko Radosavljevic, Amlan Majumdar, Brian S. Doyle, Jack T. Kavalieros, Mark L. Doczy +3 more | 2011-03-01 |
| 7883951 | CMOS device with metal and silicide gate electrodes and a method for making it | Justin K. Brask, Mark L. Doczy, Jack T. Kavalieros, Matthew V. Metz, Chris Barns +3 more | 2011-02-08 |
| 7825437 | Unity beta ratio tri-gate transistor static random access memory (SRAM) | Ravi Pillarisetty, Suman Datta, Jack T. Kavalieros, Brian S. Doyle | 2010-11-02 |
| 7820512 | Spacer patterned augmentation of tri-gate transistor gate length | Ravi Pillarisetty, Suman Datta, Jack T. Kavalieros, Brian S. Doyle | 2010-10-26 |
| 7785958 | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode | Mark L. Doczy, Justin K. Brask, Jack T. Kavalieros, Matthew V. Metz, Suman Datta +2 more | 2010-08-31 |
| 7763943 | Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin | Ravi Pillarisetty, Titash Rakshit, Jack T. Kavalieros, Brian S. Doyle | 2010-07-27 |
| 7745270 | Tri-gate patterning using dual layer gate stack | Brian S. Doyle, Jack T. Kavalieros, Been-Yih Jin | 2010-06-29 |
| 7718479 | Forming integrated circuits with replacement metal gate electrodes | Jack T. Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta +1 more | 2010-05-18 |
| 7709312 | Methods for inducing strain in non-planar transistor structures | Been-Yih Jin, Brian S. Doyle, Jack T. Kavalieros | 2010-05-04 |
| 7704835 | Method of forming a selective spacer in a semiconductor device | Rajwinder Singh, Willy Rachmady, Jack T. Kavalieros | 2010-04-27 |
| 7700470 | Selective anisotropic wet etching of workfunction metal for semiconductor devices | Willy Rachmady, Jack T. Kavalieros, Brian S. Doyle | 2010-04-20 |
| 7671471 | Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode | Justin K. Brask, Jack T. Kavalieros, Mark L. Doczy, Chris Barns, Matthew V. Metz +3 more | 2010-03-02 |
| 7666796 | Substrate patterning for multi-gate transistors | Ibrahim Ban, Allen B. Gardiner | 2010-02-23 |
| 7615441 | Forming high-k dielectric layers on smooth substrates | Justin K. Brask, Jack T. Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta +2 more | 2009-11-10 |
| 7579280 | Method of patterning a film | Justin K. Brask, Brian S. Doyle, Robert S. Chau | 2009-08-25 |
| 7575976 | Localized spacer for a multi-gate transistor | Ibrahim Ban | 2009-08-18 |
| 7550333 | Nonplanar device with thinned lower body portion and method of fabrication | Brian S. Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson | 2009-06-23 |
| 7547639 | Selective surface exposure, cleans and conditioning of the germanium film in a Ge photodetector | Justin K. Brask, Bruce A. Block | 2009-06-16 |
| 7547637 | Methods for patterning a semiconductor film | Justin K. Brask, Jack T. Kavalieros, Suman Datta, Amlan Majumdar, Robert S. Chau +1 more | 2009-06-16 |
| 7531437 | Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material | Justin K. Brask, Brian S. Doyle, Jack T. Kavalieros, Mark L. Doczy, Robert S. Chau | 2009-05-12 |
| 7528025 | Nonplanar transistors with metal gate electrodes | Justin K. Brask, Brian Dovle, Jack Kavalleros, Mark L. Doczy, Robert S. Chau | 2009-05-05 |
| 7521775 | Protection of three dimensional transistor structures during gate stack etch | Brian S. Doyle, Been-Yih Jin, Jack T. Kavalieros | 2009-04-21 |
| 7479421 | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby | Jack T. Kavalieros, Justin K. Brask, Brian S. Doyle, Suman Datta, Mark L. Doczy +2 more | 2009-01-20 |