Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10955885 | Methods and systems to control power gates during an active state of a gated domain based on load conditions of the gated domain | Michael Zelikson, Vjekoslav Svilan, Norbert Unger | 2021-03-23 |
| 10536139 | Charge-saving power-gate apparatus and method | Norbert Unger, Michael Zelikson | 2020-01-14 |
| 10228738 | Methods and systems to control power gates during an active state of a gated domain based on load conditions of the gated domain | Michael Zelikson, Vjekoslav Svilan, Norbert Unger | 2019-03-12 |
| 9966940 | Charge-saving power-gate apparatus and method | Norbert Unger, Michael Zelikson | 2018-05-08 |
| 9874925 | Method and apparatus for a zero voltage processor sleep state | Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer +1 more | 2018-01-23 |
| 9870044 | Method and apparatus for a zero voltage processor sleep state | Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer +1 more | 2018-01-16 |
| 9841807 | Method and apparatus for a zero voltage processor sleep state | Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer +1 more | 2017-12-12 |
| 9235258 | Method and apparatus for a zero voltage processor | Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer +1 more | 2016-01-12 |
| 9223389 | Method and apparatus for a zero voltage processor | Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer +1 more | 2015-12-29 |
| 9223390 | Method and apparatus for a zero voltage processor | Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer +1 more | 2015-12-29 |
| 9141180 | Method and apparatus for a zero voltage processor sleep state | Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer +1 more | 2015-09-22 |
| 8707062 | Method and apparatus for powered off processor core mode | Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer +1 more | 2014-04-22 |
| 7664970 | Method and apparatus for a zero voltage processor sleep state | Sanjeev Jahagirdar, George Varghese, John B. Conrad, Robert Milstrey, Stephen A. Fischer +1 more | 2010-02-16 |
| 7523327 | System and method of coherent data transfer during processor idle states | Leslie E. Cline, Siripong Sritanyaratana, Alon Naveh, Eric C. Samson, Michael N. Derr | 2009-04-21 |
| 7233162 | Arrangements having IC voltage and thermal resistance designated on a per IC basis | Tawfik Arabi, Hung-Piao Ma, Gregory M. Iovino, Avner Kornfeld, Gregory F. Taylor | 2007-06-19 |
| 7112979 | Testing arrangement to distribute integrated circuits | Tawfik Arabi, Hung-Piao Ma, Gregory M. Iovino, Avner Kornfeld, Gregory F. Taylor | 2006-09-26 |
| 7109737 | Arrangements having IC voltage and thermal resistance designated on a per IC basis | Tawfik Arabi, Hung-Piao Ma, Gregory M. Iovino, Avner Kornfeld, Gregory F. Taylor | 2006-09-19 |
| 6314553 | Circuit synthesis and verification using relative timing | Kenneth S. Stevens, Ran Ginosar | 2001-11-06 |
| 5978899 | Apparatus and method for parallel processing and self-timed serial marking of variable length instructions | Ran Ginosar, Rakefet Kol, Kenneth S. Stevens, Peter A. Beerel, Kenneth Yi Yun +1 more | 1999-11-02 |
| 5948096 | Apparatus and method for self-timed marking of variable length instructions having length-affecting prefix bytes | Ran Ginosar, Rakefet Kol, Kenneth S. Stevens, Peter A. Beerel, Kenneth Yi Yun +1 more | 1999-09-07 |
| 5941982 | Efficient self-timed marking of lengthy variable length instructions | Ran Ginosar, Rakefet Kol, Kenneth S. Stevens, Peter A. Beerel, Kenneth Yi Yun +1 more | 1999-08-24 |
| 5931944 | Branch instruction handling in a self-timed marking system | Ran Ginosar, Rakefet Kol, Kenneth S. Stevens, Peter A. Beerel, Kenneth Yi Yun +1 more | 1999-08-03 |
| 5574872 | Method and apparatus for controlling the saving of pipelines in pipelined processors during trap handling | Benny Lavi, Michael Kagan | 1996-11-12 |
| 5465216 | Automatic design verification | Ze'ev Shtadler | 1995-11-07 |
| 5265227 | Parallel protection checking in an address translation look-aside buffer | Leslie D. Kohn | 1993-11-23 |