Issued Patents All Time
Showing 51–75 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9678878 | Disabling cache portions during low voltage operations | Christopher B. Wilkerson, Vivek K. De, Ming Zhang, Jaume Abella, Javier Carretero Casado +3 more | 2017-06-13 |
| 9680472 | Voltage level shifter circuit | Amit R. Trivedi, Jaydeep P. Kulkarni, Carlos Tokunaga, James W. Tschanz | 2017-06-13 |
| 9666268 | Apparatus for adjusting supply level to improve write margin of a memory cell | Yih Wang, Fatih Hamzaoglu | 2017-05-30 |
| 9665144 | Methods and systems for energy efficiency and energy conservation including entry and exit latency reduction for low power states | Jawad Nasrullah, Kelvin Kwan, Jaydeep P. Kulkarni | 2017-05-30 |
| 9627039 | Apparatus for reducing write minimum supply voltage for memory | Jaydeep P. Kulkarni, James W. Tschanz, Bibiche M. Geuskens, Vivek K. De | 2017-04-18 |
| 9621163 | Current steering level shifter | Amit R. Trivedi, Jaydeep P. Kulkarni, Dinesh Somasekhar, Carlos Tokunaga, James W. Tschanz | 2017-04-11 |
| 9563263 | Graphics processor sub-domain voltage regulation | Subramaniam Maiyuran, James W. Tschanz | 2017-02-07 |
| 9385722 | Voltage level shifter circuit | Amit R. Trivedi, Jaydeep P. Kulkarni, Carlos Tokunaga, James W. Tschanz | 2016-07-05 |
| 9355694 | Assist circuit for memory | Jaydeep P. Kulkarni, Anupama A. Thaploo, Iqbal Rajwani, Kyung Hoae Koo, Eric A. Karl | 2016-05-31 |
| 9299395 | Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks | Jaydeep P. Kulkarni, Bibiche M. Geuskens, James W. Tschanz, Vivek K. De | 2016-03-29 |
| 9230636 | Apparatus for dual purpose charge pump | Pascal A. Meinerzhagen, Jaydeep P. Kulkarni, Cyrille Dray, Dinesh Somasekhar, James W. Tschanz +1 more | 2016-01-05 |
| 9153304 | Apparatus for reducing write minimum supply voltage for memory | Jaydeep P. Kulkarni, James W. Tschanz, Bibiche M. Geuskens, Vivek K. De | 2015-10-06 |
| 9111600 | Memory cell with improved write margin | Yih Wang, Fatih Hamzaoglu | 2015-08-18 |
| 8868836 | Reducing minimum operating voltage through hybrid cache design | Christopher B. Wilkerson, Alaa R. Alameldeen, Bibiche M. Geuskens, Tanay Karnik, Vivek K. De +1 more | 2014-10-21 |
| 8824198 | Circuits and methods for reducing minimum supply for register file cells | Vivek K. De, DiaaEidin S. Khalil, Moty Mehalel, George Shchupak | 2014-09-02 |
| 8769376 | Memory cell supply voltage control based on error detection | Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Vivek K. De | 2014-07-01 |
| 8762821 | Method of correcting adjacent errors by using BCH-based error correction coding | Wei Wu, Shih-Lien Linus Lu | 2014-06-24 |
| 8667367 | Memory cell supply voltage control based on error detection | Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Vivek K. De | 2014-03-04 |
| 8467263 | Memory write operation methods and circuits | Jaydeep P. Kulkarni, Bibiche M. Geuskens, Arijit Raychowdhury, Tanay Karnik, Vivek K. De | 2013-06-18 |
| 8462541 | Circuits and methods for reducing minimum supply for register file cells | Vivek K. De, DiaaEldin S. Khalil, Moty Mehalel, George Shchupak | 2013-06-11 |
| 8456923 | Register file circuits with P-type evaluation | Bibiche M. Geuskens, Ataur Patwary, Eric Kwesi Donkoh, Tanay Karnik | 2013-06-04 |
| 8291168 | Disabling cache portions during low voltage operations | Christopher B. Wilkerson, Vivek K. De, Ming Zhang, Jaume Abella, Javier Carretero Casado +3 more | 2012-10-16 |
| 8245111 | Performing multi-bit error correction on a cache line | Zeshan A. Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Dinesh Somasekhar +1 more | 2012-08-14 |
| 8111579 | Circuits and methods for reducing minimum supply for register file cells | Vivek K. De, DiaaEldin S. Khalil, Moty Mehalel, George Shchupak | 2012-02-07 |
| 8103830 | Disabling cache portions during low voltage operations | Christopher B. Wilkerson, Vivek K. De, Ming Zhang, Jaume Abella, Javier Carretero Casado +3 more | 2012-01-24 |