Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10020037 | Capacity register file | Jaume Abella, Pedro Chaparro Monferrer, Xavier Vera | 2018-07-10 |
| 9678878 | Disabling cache portions during low voltage operations | Christopher B. Wilkerson, Muhammad M. Khellah, Vivek K. De, Ming Zhang, Jaume Abella +3 more | 2017-06-13 |
| 9619309 | Enforcing different operational configurations for different tasks for failure rate based control of processors | Enric Herrero Abellanas, Xavier Vera, Nicholas Axelos, Tanausu Ramirez, Daniel Sanchez Pedreño | 2017-04-11 |
| 9608922 | Traffic control on an on-chip network | Matteo Monchiero, Enric Herrero Abellanas, Tanausu Ramirez, Xavier Vera | 2017-03-28 |
| 9405647 | Register error protection through binary translation | Xavier Vera, Matteo Monchiero, Tanausu Ramirez, Enric Herrero | 2016-08-02 |
| 9170947 | Recovering from data errors using implicit redundancy | Xavier Vera, Matteo Monchiero, Enric Herrero, Tanausu Ramirez | 2015-10-27 |
| 9075904 | Vulnerability estimation for cache memory | Xavier Vera, Tanausu Ramirez, Daniel Sanchez, Enric Herrero Abellanas, Nicholas Axelos | 2015-07-07 |
| 9071281 | Selective provision of error correction for memory | Xavier Vera, Daniel Sanchez, Tanausu Ramirez, Enric Herrero Abellanas, Nicholas Axelos | 2015-06-30 |
| 8477558 | Memory apparatuses with low supply voltages | Jaume Abella, Xavier Vera, Pedro Chaparro Monferrer, Antonio Gonzalez | 2013-07-02 |
| 8352812 | Protecting data storage structures from intermittent errors | Xavier Vera, Jaume Abella, Antonio Gonzalez | 2013-01-08 |
| 8291168 | Disabling cache portions during low voltage operations | Christopher B. Wilkerson, Muhammad M. Khellah, Vivek K. De, Ming Zhang, Jaume Abella +3 more | 2012-10-16 |
| 8103830 | Disabling cache portions during low voltage operations | Christopher B. Wilkerson, Muhammad M. Khellah, Vivek K. De, Ming Zhang, Jaume Abella +3 more | 2012-01-24 |
| 8069376 | On-line testing for decode logic | Pedro Chaparro Monferrer, Jaume Abella, Xavier Vera | 2011-11-29 |
| 7747913 | Correcting intermittent errors in data storage structures | Jaume Abella, Xavier Vera | 2010-06-29 |
| 7577015 | Memory content inverting to minimize NTBI effects | Jaume Abella, Xavier Vera, Jose-Alejandro Pineiro, Antonio Gonzalez | 2009-08-18 |