Issued Patents All Time
Showing 101–125 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7206249 | SRAM cell power reduction circuit | Dinesh Somasekhar, Yibin Ye, James W. Tschanz, Stephen H. Tang, Vivek K. De | 2007-04-17 |
| 7200068 | Multi-ported register files | Yibin Ye, Stephen H. Tang, Vivek K. De | 2007-04-03 |
| 7190286 | Single-stage and multi-stage low power interconnect architectures | Maged Ghoneima, Peter Caputa, Ram Krishnamurthy, James W. Tschanz, Yiben Ye +2 more | 2007-03-13 |
| 7183795 | Majority voter apparatus, systems, and methods | Yibin Ye, James W. Tschanz, Vivek K. De | 2007-02-27 |
| 7167397 | Apparatus and method for programming a memory array | Fabrice Paillet, Ali Keshavarzi, Dinesh Somasekhar, Yibin Ye, Stephen H. Tang +3 more | 2007-01-23 |
| 7123500 | 1P1N 2T gain cell | Yibin Ye, Dinesh Somasekhar, Fabrice Paillet, Stephen H. Tang, Ali Keshavarzi +2 more | 2006-10-17 |
| 7120072 | Two transistor gain cell, method, and system | Yibin Ye, Dinesh Somasekhar, Fabrice Paillet, Stephen H. Tang, Ali Keshavarzi +2 more | 2006-10-10 |
| 7110278 | Crosspoint memory array utilizing one time programmable antifuse cells | Ali Keshavarzi, Fabrice Paillet, Dinesh Somasekhar, Yibin Ye, Stephen H. Tang +2 more | 2006-09-19 |
| 7102358 | Overvoltage detection apparatus, method, and system | Ali Keshavarzi, Fabrice Paillet, Dinesh Somasekhar, Yibin Ye, Stephen H. Tang +2 more | 2006-09-05 |
| 7102951 | OTP antifuse cell and cell array | Fabrice Paillet, Ali Keshavarzi, Dinesh Somasekhar, Yibin Ye, Stephen H. Tang +2 more | 2006-09-05 |
| 7098507 | Floating-body dynamic random access memory and method of fabrication in tri-gate technology | Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Yibin Ye +4 more | 2006-08-29 |
| 7075821 | Apparatus and method for a one-phase write to a one-transistor memory cell array | Yibin Ye, Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet +2 more | 2006-07-11 |
| 7072205 | Floating-body DRAM with two-phase write | Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Yibin Ye +2 more | 2006-07-04 |
| 7061806 | Floating-body memory cell write | Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Yibin Ye +2 more | 2006-06-13 |
| 7057927 | Floating-body dynamic random access memory with purge line | Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Yibin Ye +2 more | 2006-06-06 |
| 7031203 | Floating-body DRAM using write word line for increased retention time | Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Yibin Ye +1 more | 2006-04-18 |
| 7020041 | Method and apparatus to clamp SRAM supply voltage | Dinesh Somasekhar, Yibin Ye, Vivek K. De, James W. Tschanz, Stephen H. Tang | 2006-03-28 |
| 7002842 | Floating-body dynamic random access memory with purge line | Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Yibin Ye +2 more | 2006-02-21 |
| 7001811 | Method for making memory cell without halo implant | Ali Keshavarzi, Stephen H. Tang, Dinesh Somasekhar, Fabrice Paillet, Yibin Ye +2 more | 2006-02-21 |
| 6992603 | Single-stage and multi-stage low power interconnect architectures | Maged Ghoneima, Peter Caputa, Ram Krishnamurthy, James W. Tschanz, Yiben Ye +2 more | 2006-01-31 |
| 6992339 | Asymmetric memory cell | Ali Keshavarzi, Stephen H. Tang, Dinesh Somasekhar, Fabrice Paillet, Yibin Ye +2 more | 2006-01-31 |
| 6985380 | SRAM with forward body biasing to improve read cell stability | Dinesh Somasekhar, Yibin Ye, Ali R. Farhang, Gunjan H. Pandya, Vivek K. De | 2006-01-10 |
| 6952376 | Method and apparatus to generate a reference value in a memory array | Dinesh Somasekhar, Yibin Ye, Fabrice Paillet, Stephen H. Tang, Ali Keshavarzi +2 more | 2005-10-04 |
| 6909652 | SRAM bit-line reduction | Yibin Ye, Dinesh Somasekhar, Vivek K. De | 2005-06-21 |
| 6906973 | Bit-line droop reduction | Dinesh Somasekhar, Yibin Ye, Fabrice Paillet, Stephen H. Tang, Ali Keshavarzi +2 more | 2005-06-14 |