Issued Patents All Time
Showing 26–50 of 203 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11144466 | Memory device with local cache array | Jongwon Lee, Vivek Kozhikkottu, Hussein Alameer | 2021-10-12 |
| 11056179 | Techniques to couple high bandwidth memory device on silicon substrate and package substrate | Chong J. Zhao, James A. McCall, Shigeki Tomishima, George Vergis | 2021-07-06 |
| 11016669 | Persistent write data for energy-backed memory | Raj K. Ramanujan, Liyong Wang, Wesley Queen | 2021-05-25 |
| 10996888 | Write credits management for non-volatile memory | Raj K. Ramanujan, Wesley Queen, Liyong Wang | 2021-05-04 |
| 10949296 | On-die ECC with error counter and internal address generation | John B. Halbert | 2021-03-16 |
| 10943640 | Apparatus, method and system for providing termination for multiple chips of an integrated circuit package | George Vergis, James A. McCall, Ge Chang | 2021-03-09 |
| 10902890 | Method, apparatus and system for a per-DRAM addressability mode | — | 2021-01-26 |
| 10884639 | Providing single data rate (SDR) mode or double data rate (DDR) mode for the command and address (CA) bus of registering clock drive (RCD) for dynamic random access memory (DRAM) | Liyong Wang, Wesley Queen | 2021-01-05 |
| 10872011 | Internal error checking and correction (ECC) with extra system bits | Bill Nale, Rajat Agarwal | 2020-12-22 |
| 10839887 | Applying chip select for memory device identification and power management control | Christopher E. Cox, Christopher P. Mozak, James A. McCall, Akshith Vasanth, Bill Nale | 2020-11-17 |
| 10810079 | Memory device error check and scrub mode and error transparency | John B. Halbert | 2020-10-20 |
| 10802532 | Techniques to mirror a command/address or interpret command/address logic at a memory device | George Vergis, Bill Nale | 2020-10-13 |
| 10789010 | Double data rate command bus | George Vergis | 2020-09-29 |
| 10680613 | Programmable on-die termination timing in a multi-rank system | Alexey Kostinsky, Nadav Bonen | 2020-06-09 |
| 10592445 | Techniques to access or operate a dual in-line memory module via multiple data channels | Bill Nale, Christopher E. Cox, George Vergis, James A. McCall, Chong J. Zhao +3 more | 2020-03-17 |
| 10552285 | Impedance compensation based on detecting sensor data | James A. McCall | 2020-02-04 |
| 10522207 | Performance of additional refresh operations during self-refresh mode | Shay Fux, John B. Halbert | 2019-12-31 |
| 10503435 | Providing extended dynamic random access memory (DRAM) burst lengths in processor-based systems | Wesley Queen, Liyong Wang | 2019-12-10 |
| 10504579 | Directed per bank refresh command | — | 2019-12-10 |
| 10496473 | Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC) | Debaleena Das, Bill Nale, John B. Halbert | 2019-12-03 |
| 10489083 | Flexible command addressing for memory | John B. Halbert | 2019-11-26 |
| 10490239 | Programmable data pattern for repeated writes to memory | Shigeki Tomishima | 2019-11-26 |
| 10310547 | Techniques to mirror a command/address or interpret command/address logic at a memory device | George Vergis, Bill Nale | 2019-06-04 |
| 10242727 | Reduction of power consumption in memory devices during refresh modes | Christopher E. Cox, John B. Halbert | 2019-03-26 |
| 10224090 | Directed per bank refresh command | — | 2019-03-05 |