Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6757784 | Hiding refresh of memory and refresh-hidden memory | Shih-Lien Linus Lu, Dinesh Somasekhar | 2004-06-29 |
| 6725341 | Cache line pre-load and pre-own based on cache coherence speculation | Jih-Kwon Peir, Steve Yu Zhang, Scott H. Robinson, Wen-Hann Wang | 2004-04-20 |
| 6711662 | Multiprocessor cache coherence management | Jih-Kwon Peir | 2004-03-23 |
| RE38388 | Method and apparatus for performing deferred transactions | Nitin V. Sarangdhar, Gurbir Singh, Peter D. MacWilliams, Stephen S. Pawlowski, Michael W. Rhodehamel | 2004-01-13 |
| 6671780 | Modified least recently allocated cache replacement method and apparatus that allows skipping a least recently allocated cache block | Shih-Lien Linus Lu | 2003-12-30 |
| 6608775 | Register file scheme | Shih-Lien Linus Lu | 2003-08-19 |
| 6507895 | Method and apparatus for access demarcation | Hong Wang, Ralph M. Kling, Jeff Baxter | 2003-01-14 |
| 6430083 | Register file scheme | Shih-Lien Linus Lu | 2002-08-06 |
| 6397291 | Method and apparatus for retrieving data from a data storage device | Randy M. Bonella, Peter D. MacWilliams | 2002-05-28 |
| 6192459 | Method and apparatus for retrieving data from a data storage device | Randy M. Bonella, Peter D. MacWilliams | 2001-02-20 |
| 6006299 | Apparatus and method for caching lock conditions in a multi-processor system | Wen-Hann Wang, Gurbir Singh, Mandar Joshi, Nitin V. Sarangdhar, Matthew A. Fisch | 1999-12-21 |
| 5966722 | Method and apparatus for controlling multiple dice with a single die | Gurbir Singh | 1999-10-12 |
| 5937171 | Method and apparatus for performing deferred transactions | Nitin V. Sarangdhar, Gurbir Singh, Peter D. MacWilliams | 1999-08-10 |
| 5903738 | Method and apparatus for performing bus transactions in a computer system | Nitin V. Sarangdhar, Gurbir Singh | 1999-05-11 |
| 5903908 | Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories | Gurbir Singh, Michael W. Rodehamel | 1999-05-11 |
| 5832534 | Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories | Gurbir Singh, Michael W. Rhodehamel | 1998-11-03 |
| 5802605 | Physical address size selection and page size selection in an address translator | Donald B. Alpert, Kenneth D. Shoemaker, Kevin C. Kahn | 1998-09-01 |
| 5796977 | Highly pipelined bus architecture | Nitin V. Sarangdhar, Gurbir Singh, Stephen S. Pawlowski, Peter D. MacWilliams, Michael W. Rhodehamel | 1998-08-18 |
| 5715428 | Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system | Wen-Hann Wang, Gurbir Singh, Michael W. Rhodehamel, Nitin V. Sarangdhar, John M. Bauer +2 more | 1998-02-03 |
| 5678020 | Memory subsystem wherein a single processor chip controls multiple cache memory chips | Gurbir Singh | 1997-10-14 |
| 5617554 | Physical address size selection and page size selection in an address translator | Donald B. Alpert, Kenneth D. Shoemaker, Kevin C. Kahn | 1997-04-01 |
| 5615343 | Method and apparatus for performing deferred transactions | Nitin V. Sarangdhar, Gurbir Singh, Peter D. MacWilliams, Stephen S. Pawlowski, Michael W. Rhodehamel | 1997-03-25 |
| 5581782 | Computer system with distributed bus arbitration scheme for symmetric and priority agents | Nitin V. Sarangdhar, Gurbir Singh, Michael W. Rhodehamel, Matthew A. Fisch | 1996-12-03 |
| 5568620 | Method and apparatus for performing bus transactions in a computer system | Nitin V. Sarangdhar, Gurbir Singh | 1996-10-22 |
| 5564035 | Exclusive and/or partially inclusive extension cache system and method to minimize swapping therein | — | 1996-10-08 |