Issued Patents All Time
Showing 26–50 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7876693 | Testing and error recovery across multiple switching fabrics | Eric T. Anderson, Philip Ferolito, Mike Morrison | 2011-01-25 |
| 7801045 | Hierarchical rate limiting with proportional limiting | Sanjay Jain | 2010-09-21 |
| 7733888 | Pointer allocation by prime numbers | Sanjay Jain, Jorge Alejandro Aguilar, Avinash Gyanendra Mani | 2010-06-08 |
| 7525917 | Flow control in a distributed scalable, shared memory switching fabric system | Philip Ferolito, Eric T. Anderson | 2009-04-28 |
| 7394822 | Using reassembly queue sets for packet reassembly | Eric T. Anderson, Philip Ferolito, Mike Morrison | 2008-07-01 |
| 7349336 | Random early drop with per hop behavior biasing | James Bauman | 2008-03-25 |
| 7242691 | Optimal load balancing across multiple switching fabrics | Eric T. Anderson, Philip Ferolito, Mike Morrison | 2007-07-10 |
| 6725339 | Processing ordered data requests to a memory | John Fu, Dean Mulla, Stuart E. Sailer, Jeng-Jye Shaw | 2004-04-20 |
| 6687790 | Single bank associative cache | Edward Zager | 2004-02-03 |
| 6681317 | Method and apparatus to provide advanced load ordering | — | 2004-01-20 |
| 6678815 | Apparatus and method for reducing power consumption due to cache and TLB accesses in a processor front-end | Edward T. Grochowski, Chih-Hung Chung | 2004-01-13 |
| 6658559 | Method and apparatus for advancing load operations | Judge K. Arora, Ghassan Khadder, Sreenivas Aerra Reddy | 2003-12-02 |
| 6625715 | System and method for translation buffer accommodating multiple page sizes | — | 2003-09-23 |
| 6567952 | Method and apparatus for set associative cache tag error detection | Nhon Quach | 2003-05-20 |
| 6560689 | TLB using region ID prevalidation | Gary N. Hammond | 2003-05-06 |
| 6542966 | Method and apparatus for managing temporal and non-temporal data in a single cache structure | John H. Crawford, Gautam Doshi, Stuart E. Sailer, John Fu | 2003-04-01 |
| 6427191 | High performance fully dual-ported, pipelined cache design | John Fu, Dean Mulla | 2002-07-30 |
| 6418521 | Hierarchical fully-associative-translation lookaside buffer structure | Dean Mulla, John Wai Cheong Fu, Stuart E. Sailer | 2002-07-09 |
| 6405233 | Unaligned semaphore adder | Jeng-Jye Shaw | 2002-06-11 |
| 6381678 | Processing ordered data requests to a memory | John Fu, Dean Mulla, Stuart E. Sailer, Jeng-Jye Shaw | 2002-04-30 |
| 6282636 | Decentralized exception processing system | Tse-Yu Yeh, Steven Tu | 2001-08-28 |
| 6275901 | Computer system having a set associative cache memory with sequentially accessed on-chip address tag array and off-chip data array | Edward Zager | 2001-08-14 |
| 6272597 | Dual-ported, pipelined, two level cache system | John Fu, Dean Mulla, Stuart E. Sailer | 2001-08-07 |
| 6233652 | Translation lookaside buffer for multiple page sizes | Jarvis Leung | 2001-05-15 |
| 6223263 | Method and apparatus for locking and unlocking a memory region | Selina Yuen | 2001-04-24 |