Issued Patents All Time
Showing 51–63 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6134636 | Method and apparatus for storing data in a memory array | John Fu, Dean Mulla | 2000-10-17 |
| 6105115 | Method and apparatus for managing a memory array | Dean Mulla | 2000-08-15 |
| 5956752 | Method and apparatus for accessing a cache using index prediction | — | 1999-09-21 |
| 5802577 | Multi-processing cache coherency protocol on a local bus | Ketan S. Bhat | 1998-09-01 |
| 5634131 | Method and apparatus for independently stopping and restarting functional units | Eugene P. Matter, Yahya S. Sotoudeh | 1997-05-27 |
| 5481697 | An apparatus for providing a clock signal for a microprocessor at a selectable one of a plurality of frequencies and for dynamically switching between any of said plurality of frequencies | Edward Zager, Sundari Mitra | 1996-01-02 |
| 5469544 | Central processing unit address pipelining | Deepak Aatresh, Tosaku Nakanishi | 1995-11-21 |
| 5398244 | Method and apparatus for reduced latency in hold bus cycles | Deepak Aatresh, Sanjay Jain | 1995-03-14 |
| 5392437 | Method and apparatus for independently stopping and restarting functional units | Eugene P. Matter, Yahya S. Sotoudeh | 1995-02-21 |
| 5359723 | Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small write back second level that allocates for CPU write misses only | Edward Zager | 1994-10-25 |
| 5278964 | Microprocessor system including a cache controller which remaps cache address bits to confine page data to a particular block of cache | Ghassan Khadder | 1994-01-11 |
| 5276888 | Computer system with interrupts transparent to its operating system and application programs | James P. Kardach, Cau L. Nguyen, Sung-Soo Cho, Kameswaran Sivamani, David S. Vannier +2 more | 1994-01-04 |
| 5175853 | Transparent system interrupt | James P. Kardach, Cau L. Nguyen, Sung-Soo Cho, Kameswaran Sivamani, David S. Vannier +2 more | 1992-12-29 |