| 6687790 |
Single bank associative cache |
Gregory S. Mathews |
2004-02-03 |
| 6275901 |
Computer system having a set associative cache memory with sequentially accessed on-chip address tag array and off-chip data array |
Gregory S. Mathews |
2001-08-14 |
| 5481697 |
An apparatus for providing a clock signal for a microprocessor at a selectable one of a plurality of frequencies and for dynamically switching between any of said plurality of frequencies |
Gregory S. Mathews, Sundari Mitra |
1996-01-02 |
| 5359723 |
Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small write back second level that allocates for CPU write misses only |
Gregory S. Mathews |
1994-10-25 |
| 5276888 |
Computer system with interrupts transparent to its operating system and application programs |
James P. Kardach, Gregory S. Mathews, Cau L. Nguyen, Sung-Soo Cho, Kameswaran Sivamani +2 more |
1994-01-04 |
| 5175853 |
Transparent system interrupt |
James P. Kardach, Gregory S. Mathews, Cau L. Nguyen, Sung-Soo Cho, Kameswaran Sivamani +2 more |
1992-12-29 |