Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small write back second level that allocates for CPU write misses only

Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small write back second level that allocates for CPU write misses only

US Patent 5359723 · Granted Oct 25, 1994

Estimated economic value: $40,369,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Handling eviction write operations caused by rate-limited traffic2025
Write arbiter circuit with per-rank allocation override mode2025
Memory device bandwidth optimization2025
Memory error tracking and logging2025
Decoding status flag techniques for memory circuits2025
Read arbiter circuit with dual memory rank support2025
Memory bank hotspotting2024
Temperature-based bandwidth compensation for memory traffic2024
Memory error tracking and logging2024
Memory device bandwidth optimization2024
Multi-activation techniques for partial write operations2023
Data corruption tracking for memory reliability2023