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USPTO Patent Rankings Data through Dec 31, 2025
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Deepak Aatresh — 12 Patents

ADAditazz: 4 patents #2 of 23Top 9%
Intel: 4 patents #8,538 of 30,777Top 30%
CSCabletron Systems: 1 patents #92 of 189Top 50%
RNRiverstone Networks: 1 patents #6 of 19Top 35%
ATAT&T: 1 patents #10,636 of 18,772Top 60%
Alcatel Lucent: 1 patents #2,436 of 1,504Top 165%
Saratoga, CA: #749 of 2,933 inventorsTop 30%
California: #51,404 of 386,348 inventorsTop 15%
Overall (All Time): #396,045 of 4,157,543Top 10%
12 Patents All Time
Deepak Aatresh has been granted 12 US patents while listed as an inventor at Aditazz. The first was granted in 1995 and the most recent in October 2019. Deepak Aatresh ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list Deepak Aatresh in Saratoga, CA, US.

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10452790 System and method for evaluating the energy use of multiple different building massing configurations Sungmin Kim, Robert C. U. Yu 2019-10-22
9721046 System and method for realizing a building system that involves computer based matching of form to function Alexander Khainson, Zachary Deretsky, Ward Vercruysse, Richard L. Sarao, Sudha Hajela 2017-08-01
9607110 System and method for realizing a building system Ward Vercruysse, Zigmund Rubel 2017-03-28
9507885 System and method for realizing a building using automated building massing configuration generation Robert C. U. Yu, Sungmin Kim 2016-11-29
7652988 Hardware-based rate control for bursty traffic Sanjay Jain, Daniel M. Hegglin 2010-01-26 $1,188,000
7352761 Distributing unused allocated bandwidth using a borrow vector Sandeep Lodha, Rajesh Narayanan, Raymond Vaughan-Williams 2008-04-01
6798741 Method and system for rate shaping in packet-based computer networks Sandeep Lodha 2004-09-28
6067301 Method and apparatus for forwarding packets from a plurality of contending queues to an output 2000-05-23 $20,878,000
5954814 System for using a branch prediction unit to achieve serialization by forcing a branch misprediction to flush a pipeline Nazar Zaidi, Michael J. Morrison 1999-09-21 $160,271,000
5586332 Power management for low power processors through the use of auto clock-throttling Sanjay Jain 1996-12-17 $98,035,000
5469544 Central processing unit address pipelining Tosaku Nakanishi, Gregory S. Mathews 1995-11-21 $132,745,000
5398244 Method and apparatus for reduced latency in hold bus cycles Gregory S. Mathews, Sanjay Jain 1995-03-14 $28,838,000