Issued Patents All Time
Showing 25 most recent of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8533401 | Implementing direct access caches in coherent multiprocessors | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Hang T. Nguyen | 2013-09-10 |
| 8265169 | Video block memory read request translation and tagging | — | 2012-09-11 |
| 8111932 | Digital image decoder with integrated concurrent image prescaler | Joseph G. Warner, Dmitrii Loukianov | 2012-02-07 |
| 8065576 | Test access port | David E. Miner, Scott W. Murray | 2011-11-22 |
| 7966477 | Power optimized replay of blocked operations in a pipilined architecture | Sujat Jamil, Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness | 2011-06-21 |
| 7957603 | Digital image decoder with integrated concurrent image prescaler | Joseph G. Warner, Dmitrii Loukianov | 2011-06-07 |
| 7952643 | Pipelining techniques for deinterlacing video information | Satyajit Mohapatra | 2011-05-31 |
| 7944502 | Pipelining techniques for deinterlacing video information | Satyajit Mohapatra | 2011-05-17 |
| 7890790 | Transactional flow management interrupt debug architecture | — | 2011-02-15 |
| 7804542 | Spatio-temporal adaptive video de-interlacing for parallel processing | Jorge E. Caviedes, Satyajit Mohapatra | 2010-09-28 |
| 7765349 | Apparatus and method for arbitrating heterogeneous agents in on-chip busses | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Hang T. Nguyen | 2010-07-27 |
| 7757046 | Method and apparatus for optimizing line writes in cache coherent systems | Sujat Jamil, Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness | 2010-07-13 |
| 7725683 | Apparatus and method for power optimized replay via selective recirculation of instructions | Sujat Jamil, Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness | 2010-05-25 |
| 7685379 | Cache memory to support a processor's power mode of operation | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness | 2010-03-23 |
| 7640387 | Method and apparatus for implementing heterogeneous interconnects | Samantha J. Edirisooriya, Gregory Tse, Sujat Jamil, David E. Miner, R. Frank O'Bleness +1 more | 2009-12-29 |
| 7634603 | System and apparatus for early fixed latency subtractive decoding | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Hang T. Nguyen | 2009-12-15 |
| 7627797 | Test access port | David E. Miner, Scott W. Murray | 2009-12-01 |
| 7620840 | Transactional flow management interrupt debug architecture | — | 2009-11-17 |
| 7487299 | Cache memory to support a processor's power mode of operation | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness | 2009-02-03 |
| 7464227 | Method and apparatus for supporting opportunistic sharing in coherent multiprocessors | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Hang T. Nguyen | 2008-12-09 |
| 7464208 | Method and apparatus for shared resource management in a multiprocessing system | Hang T. Nguyen | 2008-12-09 |
| 7428732 | Method and apparatus for controlling access to shared resources in an environment with multiple logical processors | Jason G. Sandri, Orlando Davila | 2008-09-23 |
| 7428607 | Apparatus and method for arbitrating heterogeneous agents in on-chip busses | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Hang T. Nguyen | 2008-09-23 |
| 7406553 | System and apparatus for early fixed latency subtractive decoding | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Hang T. Nguyen | 2008-07-29 |
| 7406552 | Systems and methods for early fixed latency subtractive decoding including speculative acknowledging | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Hang T. Nguyen | 2008-07-29 |