Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7404043 | Cache memory to support a processor's power mode of operation | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness | 2008-07-22 |
| 7366845 | Pushing of clean data to one or more processors in a system having a coherency protocol | Sujat Jamil, Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness | 2008-04-29 |
| 7353317 | Method and apparatus for implementing heterogeneous interconnects | Samantha J. Edirisooriya, Gregory Tse, Sujat Jamil, David E. Miner, R. Frank O'Bleness +1 more | 2008-04-01 |
| 7290093 | Cache memory to support a processor's power mode of operation | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness | 2007-10-30 |
| 7234028 | Power/performance optimized cache using memory write prevention through write snarfing | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness | 2007-06-19 |
| 7219176 | System and apparatus for early fixed latency subtractive decoding | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Hang T. Nguyen | 2007-05-15 |
| 7216252 | Method and apparatus for machine check abort handling in a multiprocessing system | Hang T. Nguyen | 2007-05-08 |
| 7194671 | Mechanism handling race conditions in FRC-enabled processors | Alexander J. Honcharik, Hang T. Nguyen, Sujat Jamil, Quinn W. Merrell | 2007-03-20 |
| 7159077 | Direct processor cache access within a system having a coherent multi-processor protocol | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Hang T. Nguyen | 2007-01-02 |
| 7143220 | Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Hang T. Nguyen | 2006-11-28 |
| 7139947 | Test access port | David E. Miner, Scott W. Murray | 2006-11-21 |
| 7124224 | Method and apparatus for shared resource management in a multiprocessing system | Hang T. Nguyen | 2006-10-17 |
| 7100001 | Methods and apparatus for cache intervention | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Mark Fullerton +1 more | 2006-08-29 |
| 7062613 | Methods and apparatus for cache intervention | Sujat Jamil, Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness | 2006-06-13 |
| 7055060 | On-die mechanism for high-reliability processor | Hang T. Nguyen, Alexander J. Honcharik, Sujat Jamil | 2006-05-30 |
| 6983348 | Methods and apparatus for cache intervention | Sujat Jamil, Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness | 2006-01-03 |
| 6954886 | Deterministic hardware reset for FRC machine | Hang T. Nguyen | 2005-10-11 |
| 6775748 | Methods and apparatus for transferring cache block ownership | Sujat Jamil, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness | 2004-08-10 |
| 6684346 | Method and apparatus for machine check abort handling in a multiprocessing system | Hang T. Nguyen | 2004-01-27 |
| 6412062 | Injection control mechanism for external events | Yan Xu | 2002-06-25 |
| 6282636 | Decentralized exception processing system | Tse-Yu Yeh, Gregory S. Mathews | 2001-08-28 |