Issued Patents All Time
Showing 1–25 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9934152 | Method and apparatus to use hardware alias detection and management in a virtually indexed physically tagged cache | Richard Bryant, Sujat Jamil, Kim Schuttenberg | 2018-04-03 |
| 9892051 | Method and apparatus for use of a preload instruction to improve efficiency of cache | Sujat Jamil, Russell J. Robideau, Tom Hameenanttila, Joseph Delgross, David E. Miner | 2018-02-13 |
| 9842051 | Managing aliasing in a virtually indexed physically tagged cache | Kim Schuttenberg, Richard Bryant, Sujat Jamil | 2017-12-12 |
| 9606800 | Method and apparatus for sharing instruction scheduling resources among a plurality of execution threads in a multi-threaded processor architecture | Tom Hameenanttila, Sujat Jamil, Joseph Delgross | 2017-03-28 |
| 9442735 | Method and apparatus for processing speculative, out-of-order memory access instructions | Sujat Jamil, Tom Hameenanttila, Joseph Delgross | 2016-09-13 |
| 9223709 | Thread-aware cache memory management | Sujat Jamil, Tom Hameenanttila, Joseph Delgross | 2015-12-29 |
| 9141543 | Systems and methods for writing data from a caching agent to main memory according to a pre-clean criterion | Kim Schuttenberg | 2015-09-22 |
| 9116742 | Systems and methods for reducing interrupt latency | Kim Schuttenberg, Sujat Jamil | 2015-08-25 |
| 9086976 | Method and apparatus for associating requests and responses with identification information | Sujat Jamil, David E. Miner, Tom Hameenanttila, Jeffrey Kehl, Richard Bryant +1 more | 2015-07-21 |
| 9026769 | Detecting and reissuing of loop instructions in reorder structure | Sujat Jamil, Joseph Delgross, Tom Hameenanttila | 2015-05-05 |
| 8990505 | Cache memory bank selection | Sujat Jamil, David E. Miner, Joseph Delgross, Tom Hameenanttila | 2015-03-24 |
| 8943273 | Method and apparatus for improving cache efficiency | Sujat Jamil, Russell J. Robideau, Tom Hameenanttila, Joseph Delgross, David E. Miner | 2015-01-27 |
| 8918625 | Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparison | Sujat Jamil, Tom Hameenanttila | 2014-12-23 |
| 8806181 | Dynamic pipeline reconfiguration including changing a number of stages | Sujat Jamil, Timothy S. Beatty, Franco Ricci, Tom Hameenanttila, Hong-Yi Chen | 2014-08-12 |
| 8769204 | Programmable cache access protocol to optimize power consumption and performance | Joseph Delgross, Sujat Jamil, Tom Hameenanttila, David E. Miner | 2014-07-01 |
| 8688919 | Method and apparatus for associating requests and responses with identification information | Sujat Jamil, David E. Miner, Tom Hameenanttila, Jeffrey Kehl, Richard Bryant +1 more | 2014-04-01 |
| 8631206 | Way-selecting translation lookaside buffer | Sujat Jamil, David E. Miner, Joseph Delgross, Tom Hameenanttila | 2014-01-14 |
| 8533401 | Implementing direct access caches in coherent multiprocessors | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Steven Tu, Hang T. Nguyen | 2013-09-10 |
| 8458404 | Programmable cache access protocol to optimize power consumption and performance | Joseph Delgross, Sujat Jamil, Tom Hameenanttila, David E. Miner | 2013-06-04 |
| 8135916 | Method and apparatus for hardware-configurable multi-policy coherence protocol | Sujat Jamil, David E. Miner, Joseph Delgross, Tom Hameenanttila, Jeffrey Kehl | 2012-03-13 |
| 7966477 | Power optimized replay of blocked operations in a pipilined architecture | Sujat Jamil, Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, Steven Tu | 2011-06-21 |
| 7765349 | Apparatus and method for arbitrating heterogeneous agents in on-chip busses | Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, Steven Tu, Hang T. Nguyen | 2010-07-27 |
| 7757046 | Method and apparatus for optimizing line writes in cache coherent systems | Sujat Jamil, Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, Steven Tu | 2010-07-13 |
| 7725683 | Apparatus and method for power optimized replay via selective recirculation of instructions | Sujat Jamil, Hang T. Nguyen, Samantha J. Edirisooriya, David E. Miner, Steven Tu | 2010-05-25 |
| 7694080 | Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput | Quinn W. Merrell, Sujat Jamil, Hang T. Nguyen | 2010-04-06 |