Issued Patents All Time
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12353885 | Speculative execution following a state transition instruction | Rong Zhang | 2025-07-08 |
| 12293189 | Data value prediction and pre-alignment based on prefetched predicted memory access address | Richard Bryant | 2025-05-06 |
| 11301252 | Executing mutually exclusive vector instructions according to a vector predicate instruction | — | 2022-04-12 |
| 11132200 | Loop end prediction using loop counter updated by inflight loop end instructions | Vijay Chavan, Rong Zhang | 2021-09-28 |
| 11086777 | Replacement of cache entries in a set-associative cache | — | 2021-08-10 |
| 10901691 | System, method and apparatus for inter-process communication | Jonathan Curtis Beard, Syed Ali Mustafa Zaidi | 2021-01-26 |
| 10877901 | Method and apparatus for utilizing proxy identifiers for merging of store operations | Richard Bryant, Lilian Atieno Hutchins, Thomas Edward Roberts, Alex James Waugh, Max John Batley | 2020-12-29 |
| 10545879 | Apparatus and method for handling access requests | Richard Bryant, David Madsen, Lalit Bansal, Sriram Samynathan | 2020-01-28 |
| 10474469 | Apparatus and method for determining a recovery point from which to resume instruction execution following handling of an unexpected change in instruction flow | — | 2019-11-12 |
| 9934152 | Method and apparatus to use hardware alias detection and management in a virtually indexed physically tagged cache | Richard Bryant, R. Frank O'Bleness, Sujat Jamil | 2018-04-03 |
| 9842051 | Managing aliasing in a virtually indexed physically tagged cache | Richard Bryant, Sujat Jamil, R. Frank O'Bleness | 2017-12-12 |
| 9645936 | System and method for informing hardware to limit writing in a memory hierarchy | Richard Bryant | 2017-05-09 |
| 9436210 | Control—mechanism for selectively shorting clock grid by electrically connecting and disconnecting clock branches once per clock cycle | Franco Ricci | 2016-09-06 |
| 9405542 | Method and apparatus for updating a speculative rename table in a microprocessor | Sridharan Balasubramanian | 2016-08-02 |
| 9367456 | Integrated circuit and method for accessing segments of a cache line in arrays of storage elements of a folded cache | Richard Bryant | 2016-06-14 |
| 9360915 | Dynamically controlling clocking rate of a processor based on user defined rule | — | 2016-06-07 |
| 9311247 | Method and apparatus for detecting patterns of memory accesses in a computing system with out-of-order program execution | — | 2016-04-12 |
| 9304693 | System and method for writing data to a data storage structure | — | 2016-04-05 |
| 9304777 | Method and apparatus for determining relative ages of entries in a queue | Sridharan Balasubramanian | 2016-04-05 |
| 9164900 | Methods and systems for expanding preload capabilities of a memory to encompass a register file | — | 2015-10-20 |
| 9141543 | Systems and methods for writing data from a caching agent to main memory according to a pre-clean criterion | R. Frank O'Bleness | 2015-09-22 |
| 9116742 | Systems and methods for reducing interrupt latency | Sujat Jamil, R. Frank O'Bleness | 2015-08-25 |
| 9086976 | Method and apparatus for associating requests and responses with identification information | R. Frank O'Bleness, Sujat Jamil, David E. Miner, Tom Hameenanttila, Jeffrey Kehl +1 more | 2015-07-21 |
| 8688919 | Method and apparatus for associating requests and responses with identification information | R. Frank O'Bleness, Sujat Jamil, David E. Miner, Tom Hameenanttila, Jeffrey Kehl +1 more | 2014-04-01 |
| 8607090 | Selective shorting for clock grid during a controlling portion of a clock signal | Franco Ricci | 2013-12-10 |