Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11301253 | Branch prediction structure indexed based on return address popped from a call-return stack | Varun Palivela | 2022-04-12 |
| 9892051 | Method and apparatus for use of a preload instruction to improve efficiency of cache | Sujat Jamil, R. Frank O'Bleness, Russell J. Robideau, Joseph Delgross, David E. Miner | 2018-02-13 |
| 9619402 | Method and apparatus for optimizing translation of a virtual memory address into a physical memory address in a processor having virtual memory | Rong Zhang, Frank O'Bleness | 2017-04-11 |
| 9606800 | Method and apparatus for sharing instruction scheduling resources among a plurality of execution threads in a multi-threaded processor architecture | R. Frank O'Bleness, Sujat Jamil, Joseph Delgross | 2017-03-28 |
| 9442735 | Method and apparatus for processing speculative, out-of-order memory access instructions | Sujat Jamil, R. Frank O'Bleness, Joseph Delgross | 2016-09-13 |
| 9223709 | Thread-aware cache memory management | R. Frank O'Bleness, Sujat Jamil, Joseph Delgross | 2015-12-29 |
| 9195524 | Hardware support for performance analysis | Robert Wiesner | 2015-11-24 |
| 9086976 | Method and apparatus for associating requests and responses with identification information | R. Frank O'Bleness, Sujat Jamil, David E. Miner, Jeffrey Kehl, Richard Bryant +1 more | 2015-07-21 |
| 9058272 | Method and apparatus having a snoop filter decoupled from an associated cache and a buffer for replacement line addresses | Frank O'Bleness, Sujat Jamil, David E. Miner, Joseph Delgross, Jeffrey Kehl +1 more | 2015-06-16 |
| 9026769 | Detecting and reissuing of loop instructions in reorder structure | Sujat Jamil, R. Frank O'Bleness, Joseph Delgross | 2015-05-05 |
| 8990505 | Cache memory bank selection | Sujat Jamil, R. Frank O'Bleness, David E. Miner, Joseph Delgross | 2015-03-24 |
| 8943273 | Method and apparatus for improving cache efficiency | Sujat Jamil, R. Frank O'Bleness, Russell J. Robideau, Joseph Delgross, David E. Miner | 2015-01-27 |
| 8918625 | Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparison | R. Frank O'Bleness, Sujat Jamil | 2014-12-23 |
| 8806181 | Dynamic pipeline reconfiguration including changing a number of stages | R. Frank O'Bleness, Sujat Jamil, Timothy S. Beatty, Franco Ricci, Hong-Yi Chen | 2014-08-12 |
| 8769204 | Programmable cache access protocol to optimize power consumption and performance | Joseph Delgross, Sujat Jamil, R. Frank O'Bleness, David E. Miner | 2014-07-01 |
| 8688919 | Method and apparatus for associating requests and responses with identification information | R. Frank O'Bleness, Sujat Jamil, David E. Miner, Jeffrey Kehl, Richard Bryant +1 more | 2014-04-01 |
| 8631206 | Way-selecting translation lookaside buffer | R. Frank O'Bleness, Sujat Jamil, David E. Miner, Joseph Delgross | 2014-01-14 |
| 8458404 | Programmable cache access protocol to optimize power consumption and performance | Joseph Delgross, Sujat Jamil, R. Frank O'Bleness, David E. Miner | 2013-06-04 |
| 8296525 | Method and apparatus for data-less bus query | Frank O'Bleness, Sujat Jamil, David E. Miner, Jeffrey Kehl, Richard Bryant +1 more | 2012-10-23 |
| 8135916 | Method and apparatus for hardware-configurable multi-policy coherence protocol | R. Frank O'Bleness, Sujat Jamil, David E. Miner, Joseph Delgross, Jeffrey Kehl | 2012-03-13 |
| 6611856 | Processing multiply-accumulate operations in a single cycle | Yuyun Liao, David B. Roberts | 2003-08-26 |