Issued Patents All Time
Showing 25 most recent of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12377979 | Unmanned food delivery device in cabin and application method thereof | Shun Jia, Shang WANG, Na Zhang, Tianyou Hou, Bo Yang +7 more | 2025-08-05 |
| 12360904 | Fast synchronization mechanism for heterogeneous computing | Hsing-Chuang Liu, Yu-Shu Chen | 2025-07-15 |
| 9765444 | Continuous electrochemical machining apparatus | YOU-LUN CHEN, DA-YU LIN, Ho-Chung Fu | 2017-09-19 |
| 9608541 | DC-to-AC conversion apparatus and method of operating the same | Wei-Lun Hsin | 2017-03-28 |
| 9306474 | Power conversion system and method of operating the same | Chen-Wei Ku, Wei-Lun Hsin | 2016-04-05 |
| 9158355 | Dynamic core switching | Sehat Sutardja, Premanand Sakarda, Mark Fullerton, Jay Heeb | 2015-10-13 |
| 8935591 | System and method to correct errors in data read from a source supplying streaming data | Pantas Sutardja | 2015-01-13 |
| 8909903 | Providing data to registers between execution stages | Jensen Tjeng | 2014-12-09 |
| 8874948 | Apparatuses for operating, during respective power modes, transistors of multiple processors at corresponding duty cycles | Sehat Sutardja | 2014-10-28 |
| 8806181 | Dynamic pipeline reconfiguration including changing a number of stages | R. Frank O'Bleness, Sujat Jamil, Timothy S. Beatty, Franco Ricci, Tom Hameenanttila | 2014-08-12 |
| 8667370 | Systems and methods for arbitrating use of processor memory | Pantas Sutardja | 2014-03-04 |
| 8621152 | Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access | Geoffrey K. Yung | 2013-12-31 |
| 8572416 | Low power computer with main and auxiliary processors | Sehat Sutardja | 2013-10-29 |
| 8526257 | Processor with memory delayed bit line precharging | Sehat Sutardja, Jason Su, Jason Sheu, Jensen Tjeng | 2013-09-03 |
| 8468324 | Dual thread processor | Sehat Sutardja | 2013-06-18 |
| 8392799 | Systems and methods for arbitrating use of processor memory | Pantas Sutardja | 2013-03-05 |
| 8347034 | Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access | Geoffrey K. Yung | 2013-01-01 |
| 8295110 | Processor instruction cache with dual-read modes | Sehat Sutardja, Jason Su, Jason Sheu, Jensen Tjeng | 2012-10-23 |
| 8195922 | System for dynamically allocating processing time to multiple threads | Sehat Sutardja | 2012-06-05 |
| 8176386 | Systems and methods for processing streaming data | Pantas Sutardja | 2012-05-08 |
| 8089823 | Processor instruction cache with dual-read modes | Sehat Sutardja, Jason Su, Jason Sheu, Jensen Tjeng | 2012-01-03 |
| 8078828 | Memory mapped register file | Henry Fan | 2011-12-13 |
| 8074056 | Variable length pipeline processor architecture | Jensen Tjeng | 2011-12-06 |
| 8043872 | Epitaxial material used for GaN based LED with low polarization effect and manufacturing method thereof | Haiqiang Jia, Liwei Guo, Wenxin Wang, Junming Zhou | 2011-10-25 |
| 8027218 | Processor instruction cache with dual-read modes | Sehat Sutardja, Jason Su, Jason Sheu, Jensen Tjeng | 2011-09-27 |