Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8621152 | Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access | Hong-Yi Chen | 2013-12-31 |
| 8347034 | Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access | Hong-Yi Chen | 2013-01-01 |
| 7984246 | Multicore memory management system | CHIA-HUNG CHIEN | 2011-07-19 |
| 7949833 | Transparent level 2 cache controller | Hong-Yi Chen | 2011-05-24 |
| 7730285 | Data processing system with partial bypass reorder buffer and combined load/store arithmetic logic unit and processing method thereof | Hong-Yi Chen, Richard Lee, Jensen Tjeng | 2010-06-01 |
| 7730261 | Multicore memory management system | CHIA-HUNG CHIEN | 2010-06-01 |
| 7685372 | Transparent level 2 cache controller | Hong-Yi Chen | 2010-03-23 |
| 7096345 | Data processing system with bypass reorder buffer having non-bypassable locations and combined load/store arithmetic logic unit and processing method thereof | Hong-Yi Chen, Richard Lee, Jensen Tjeng | 2006-08-22 |