| 8909903 |
Providing data to registers between execution stages |
Hong-Yi Chen |
2014-12-09 |
| 8526257 |
Processor with memory delayed bit line precharging |
Sehat Sutardja, Jason Su, Hong-Yi Chen, Jason Sheu |
2013-09-03 |
| 8295110 |
Processor instruction cache with dual-read modes |
Sehat Sutardja, Jason Su, Hong-Yi Chen, Jason Sheu |
2012-10-23 |
| 8089823 |
Processor instruction cache with dual-read modes |
Sehat Sutardja, Jason Su, Hong-Yi Chen, Jason Sheu |
2012-01-03 |
| 8074056 |
Variable length pipeline processor architecture |
Hong-Yi Chen |
2011-12-06 |
| 8027218 |
Processor instruction cache with dual-read modes |
Sehat Sutardja, Jason Su, Hong-Yi Chen, Jason Sheu |
2011-09-27 |
| 7787324 |
Processor instruction cache with dual-read modes |
Sehat Sutardja, Jason Su, Hong-Yi Chen, Jason Sheu |
2010-08-31 |
| 7730285 |
Data processing system with partial bypass reorder buffer and combined load/store arithmetic logic unit and processing method thereof |
Hong-Yi Chen, Richard Lee, Geoffrey K. Yung |
2010-06-01 |
| 7096345 |
Data processing system with bypass reorder buffer having non-bypassable locations and combined load/store arithmetic logic unit and processing method thereof |
Hong-Yi Chen, Richard Lee, Geoffrey K. Yung |
2006-08-22 |
