Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8526257 | Processor with memory delayed bit line precharging | Sehat Sutardja, Jason Su, Hong-Yi Chen, Jensen Tjeng | 2013-09-03 |
| 8295110 | Processor instruction cache with dual-read modes | Sehat Sutardja, Jason Su, Hong-Yi Chen, Jensen Tjeng | 2012-10-23 |
| 8089823 | Processor instruction cache with dual-read modes | Sehat Sutardja, Jason Su, Hong-Yi Chen, Jensen Tjeng | 2012-01-03 |
| 8027218 | Processor instruction cache with dual-read modes | Sehat Sutardja, Jason Su, Hong-Yi Chen, Jensen Tjeng | 2011-09-27 |
| 7787324 | Processor instruction cache with dual-read modes | Sehat Sutardja, Jason Su, Hong-Yi Chen, Jensen Tjeng | 2010-08-31 |