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Control—mechanism for selectively shorting clock grid by electrically connecting and disconnecting clock branches once per clock cycle |
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Dynamic pipeline reconfiguration including changing a number of stages |
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2014-08-12 |
| 8607090 |
Selective shorting for clock grid during a controlling portion of a clock signal |
Kim Schuttenberg |
2013-12-10 |
| 7796445 |
State-retentive scan latch |
Manish Biyani |
2010-09-14 |
| 7200060 |
Memory driver architecture and associated methods |
Timothy S. Beatty, Lawrence T. Clark |
2007-04-03 |
| 6774696 |
Level shifter and voltage translator |
Lawrence T. Clark, Shay Demmons, Tim Beatty |
2004-08-10 |
| 6775180 |
Low power state retention |
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2004-08-10 |
| 6639827 |
Low standby power using shadow storage |
Lawrence T. Clark |
2003-10-28 |
| 5909702 |
Memory address translations for programs code execution/relocation |
Marc Jalfon, David Regenold, Ramprasad Satagopan |
1999-06-01 |
